Intel Corporation

Bay Microsystems, Inc.

Ryszard Bleszynski

Simon S Chong

Man Dieu Trinh

Anguo Tony Huang

David A Stelliga

Barry T Lee

Golchiro Ono

An embodiment of this invention pertains to a system and method for balancing memory accesses to a low cost memory unit in order to sustain and guarantee a desired line rate regardless of the incoming traffic pattern. The memory unit may include, for example, a group of dynamic random access memory units. The memory unit is divided into memory channels and each of the memory channels is further divided into memory lines, each of the memory lines includes one or more buffers that correspond to the memory channels. The determination as to which of one or more buffers within a memory line an incoming information element is stored is based on factors such as the number of buffers pending to be read within each of the memory channels, the number of buffers pending to be written within each of the memory channels, and the number of buffers within each of the memory channels that has data written to it and is waiting to be read.

Memory management system and algorithm for network processor architecture

An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined 'multiple instruction single date' ('MISD') architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.

Vertical instruction and data processing in a network processor architecture

Systems and methods for maintaining cell transmissions at or above the minimum cell transfer rate for ABR-category VCs. An ABR schedule table (AST) in a memory stores ABR VCs scheduled for transmissions. A pointer to the AST indicates that the ABR VC currently addresses is ready to transmit a cell. The schedule pointer is incremented every cell transmission time. When a cell of a particular VC is sent, the VC is rescheduled in another time slot in the AST such that the next cell for that VC is transmitted at close to or equal to that VC's allowed cell transfer rate (ACR) while maintaining its minimum cell transfer rate (MCR). To determine the next time slot in which to reschedule the VC, the system uses an ACR bitmap that compresses the AST and which identifies entries that are not occupied by a VC scheduled for a transmission. The system determines the time slot in the AST that would allow the VC to be transmitted at its ACR. The system then checks the ACR bitmap to determine whether that ACR slot is unoccupied. If occupied, the system searches the ACR bitmap to locate the next empty slot in the AST. If all slots between the ACR slot and the slot which provides for an MCR transmission for that VC are occupied, the system searches an MCR bitmap, which compresses the AST, to determine which VC occupying the AST between the ACR slot and the MCR slot is to be replaced by the VC being rescheduled. The VC that is replaced is itself rescheduled. In this manner MCR is guaranteed for a VC being rescheduled.

Systems and methods for implementing ABR with guaranteed MCR

Systems and methods for assisting multiple protocol conversion in a network accelerator. A network device includes a transmit processing engine, a receive processing engine and one or more memories, each memory including one or more buffers for storing packets. When a packet is received, the receive engine adds a 4, 8, 12 or 16-byte tag to the front of the packet on a per-VC basis and stores the packet to a buffer. Additionally, the receive engine is able to add an offset to the starting address of the packet in the buffer relative to the beginning of the buffer. When a packet is to be transmitted, the transmit engine is able to transmit the packet from an address that is offset from the starting address of the buffer by one or more bytes. Additionally, the transmit engine is able to add one of several predefined packet headers on a per-packet basis.

Multi-protocol conversion assistance method and system for a network accelerator

A CBR/VBR traffic scheduler includes multiple CBR/VBR shapers to shape traffic over a wide range of peak cell rates for multiple CBR and VBR connection. Each shaper points to one or more VCs in a link list and includes a PCR counter initialized to a first value, an SCR counter initialized to a second and an arbitration counter. Each shaper is also connected to one of several clock sources, each having an associated clock cycle. A priority encoder, coupled to each arbitration counter, provides for determining priority between shapers having one or more associated VCs ready for transmission. Both the PCR counter and the SCR counter for each shaper is decremented during each associated clock cycle. For each shaper, when the PCR counter is decremented to a value of zero, the arbitration counter is initialized to a preset value and enabled for selection by the priority encoder. For each shaper, when the SCR counter is decremented to zero, a credit count parameter associated with each of the VCs in the associated link list is incremented by a predetermined value. The shaper having the lowest arbitration count value is selected by the priority encoder for cell transmission. When a shaper is selected for cell transmission, the associated link list of VCs is walked through in order. Only VCs that have a credit count parameter above a threshold value are transmitted.

CBR/VBR traffic scheduler

Systems and methods for storing, or caching, VC descriptors on a single-chip network processor to enhance system performance. The single-chip network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory. In this manner, VC descriptors associated with high bandwidth VCs are stored to the cache and retrieved much quicker from the cache than from the off-chip memory.

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Cupertino, CA, United States of America

Ryszard Bleszynski