Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Computer Engineering Co., Ltd.

Ryozo Yoshino

Takashi Suga

Yoshihiko Hayashi

Masami Makuuchi

Kouichi Uesaka

Masato Hirai

Hideo Miura

Hiroyuki Ohta

Koji Sasaki

Kunio Matsumoto

Norihiko Sugimoto

Mitsuhiro Yamaga

Shigeo Nishita

Kazunori Nakamura

Naoto Saito

Masami Kurata

An IC card has an IC chip and a circuit layer formed between layers of a base material that are adhered together by an adhesive. The IC card has a thickness of 0.25 to 0.76 mm and therefore the thickness of the IC chip needs to be about 0.2 mm, which requires grinding of the IC chip. In use, the IC card is subject to bending forces which apply a bending stress on the chip. In the process of grinding the IC chip, grinding flaws having sharp parts arise that reduce the bending strength of the chip. Also, during the dicing process of the wafer, chipping occurs that results in notches having sharp tip parts being formed in the chip. The grinding flaws that result from the grinding and the notches that result from the chipping are etched to remove their sharpness, which occurs at the tip part of the grinding flaw or the tip part of the notch. By rounding these sharp parts through the etching step, the bending strength of the IC chip increases and the durability of the IC card is ensured.

IC card and its manufacturing method

The present invention provides a reader and/or writer for performing both the supply of operating power to an IC card and transmission of a communication signal to the IC card or transmission and reception thereof to and from the IC card, wherein a main coil or a spiral antenna for generating an electromagnetic field for the two or at least power supply, and auxiliary coils or spiral antennas for generating magnetic fields opposite in phase to the electromagnetic field generated by the main coil or spiral antenna to thereby restrain the intensity of the electromagnetic field in the distance are provided side by side.

Reader/writer having coil arrangements to restrain electromagnetic field intensity at a distance

The present invention provides a power transmission/communication system for transmitting power from a reader and/or writer to an IC card by an electromagnetic wave and performing transmission or transmission and reception of a communication signal between the reader and/or writer and the IC card by an electromagnetic wave, wherein the intensity of a magnetic field induced by the electromagnetic wave outputted from the reader and/or writer, i.e., the magnitude of power induced thereby and the time required to transmit the power are controlled.

Power transmission system, power transmission/communication system and

The data input/output circuit for full duplex communication includes a data accepting and sending circuit which has an input/output terminal connected to a processor provided within a digital apparatus, and which receives data from the processor, transmits the data and receives outside data through the input/output terminal, a reference circuit which divides a voltage level of the data transmitted from the data accepting and sending circuit and produces a divided voltage level, a differential receiving circuit which has one input terminal connected to the input/output terminal and another input terminal connected to the reference circuit, and which is not operated by a zero voltage difference between the input terminals when the data is transmitted from the input/output terminal but operated by a voltage difference between the input terminals when the data is received through the input/output terminal, the data being supplied to the processor of the digital apparatus, a reference circuit for generating an output impedance value of the data accepting and sending circuit, and a voltage regulation circuit for adjusting a power supply voltage to be applied to the data accepting and sending circuit so that the output impedance value is changed in accordance with the value of the output impedance. This data input/output circuit can be incorporated in an LSI of CMOS transistor structure and has a simple circuit arrangement capable of impedance matching with the transmission path.

CMOS full duplex transmission-reception circuit

A transmission-reception circuit, including a transmitter circuit and a receiver circuit connected to each end of a transmission line, for transmitting and receiving a signal to another receiver circuit and from another transmitter circuit at the other end across the transmission line, wherein in order to enable logical decision on a receiving signal to be made accurately and secure high reliability in a fully duplex simultaneous two-way communication, power supply lines are laid at opposite ends of the transmission line and threshold voltages for logical decision on a signal received by the receiver circuit are supplied from a power unit used for the transmitter circuit and the receiver circuit at the other end of the transmission line.

Transmission-reception circuit

A PLL circuit for generating an AC output signal synchronized with an AC input signal applied thereto with a phase offset with respect to the input signal includes, in one embodiment, a charge pump circuit capable of varying the phase offset depending on the frequency of the AC input signal. In a signal transmission network system including a plurality of nodes coupled to a signal transmission line and distanced from one another by various repeat lengths of transmission path, each node has a repeater including such PLL circuit to suppress jitter caused by individual repeat length of transmission over the transmission line and still remaining in an equalized AC signal in each node.

Repeater and PLL circuit

A multiple reproducing repeater station system having a plurality of repeater stations connected in tandem. Each of the repeater stations comprises a logical circuit for decoding data from a pulse-modulated signal transmitted from the preceding repeater station and delivering decoded data to a processing circuit, and a PLL for extracting a clock signal from the pulse-modulated signal. The PLL has an operational response time which is so adjusted as to be different from a data delay time due to a logical operation within the logical circuit.

Multiple reproducing repeater station system

A relay circuit comprise first and second relays having respective terminals at which positive cross-talk of a signal of positive polarity is produced when the other terminals to which the positive polarity signal is applied are in the make and break states, respectively, and third and fourth relays having respective terminals at which negative cross-talk of a signal of negative polarity is produced when the other terminals to which the negative polarity signal is applied are in the make and break states, respectively, wherein with regards to the terminals where the cross-talk occurs, the first and fourth relays are connected to each other and said second and third relays are connected to each other, respectively.

Trunk coupling unit

A decoding circuit is operative to decode a differential Manchester code consisting of four symbols 'J', 'K', '1' and '0' each composed of two consecutive signal elements. For detection of the symbol 'J' and consequent determination of the symbol boundary, the decoding circuit has a circuit configuration which takes advantage of the fact that the symbol 'K' immediately follows the symbol 'J' and three consecutive signal elements, two of which are included in the symbol 'J' and one of which is for a symbol immediately preceding the symbol 'J', have the same polarity. To prevent an error that a second occurrence of the symbol 'J' is detected after completion of detection of the symbol 'J', the decoding circuit has an additional circuit configuration which inhibits the detection of the symbol 'J' until the symbol '0' or the symbol '1', for example, is detected.

Growing community of inventors

Hadano, Japan

Ryozo Yoshino