Fujitsu Corporation

Ryouzi Takano

Takashi Hatano

Sumie Morita

Kiyohumi Mitsuze

Yoshiharu Kato

Takashi Nara

Katsuaki Akama

Kenichi Okabe

Hisashi Koga

Yoshio Morita

Masataka Sakai

Tsutomu Shiomitsu

Hiroyo Masuko

Ang Kar Keong

An ATM switch system performs a DMA (direct memory access) transfer of a command and status data between a call processor and a processor of a communications control device via a peripheral interface. An inter-processor DMA transfer controller of the communications control device controls a DMA transfer between its memory and the main memory of a call processor for expediting communications between the two processors.

Communications control system for transferring commands/status data in

A subscriber line control device utilizes a scan input table and a last look table. The scan input table stores respective current line states of a plurality of analog subscriber lines. The last look table stores respective preceding line states of the plurality of analog subscriber lines and information for validating or invalidating a timer device. A valid timer device corresponds to when a monitoring process is required. The scan input table is compared with the last look table at every predetermined cycle. When they do not match, it is judged whether the line state has changed or if the timer device is validated. Based on the judging result, an analog subscriber line control is performed according to an instruction specified by a call processing unit. The analog subscriber control is any of a call origination monitor, a dial pulse monitor, and an on-hook and off-hook (HIT) monitor.

Subscriber line control apparatus to concurrently detect change in line

A data transfer system including an exchange, wherein the exchange transfers data by sharing a plurality of channels by a time division multiplex mode. In this case, the exchange transfers the data by variably allocating respective time slots to be occupied by the respective channels. That is, it is possible to allot any line speed to any channel and therefore possible to mix signals with different data transfer speeds in the frames. This results in an exchange network with a high degree of freedom of transfer for the subscriber terminal equipment.

Data transfer system including exchange

A packet data switching system having packet switching equipment and a plurality of transfer control units cooperating with the packet switching equipment exchanging packet data to be transferred through the transfer control units. In the system each packet data is divided into packet frames each having the same frame length and all the packet frames are processed synchronously in each of the transfer control units. Each of the packet frames is composed of a header area and data area. The header area is used for indicating transfer control information, such as an address of a destination transfer control unit and a continuous transmission flag which denotes that the related packet frame should be exchanged to the same destination as that of the preceding packet frame.

Packet data switching system

A maintenance link is established according to a LAPD between first and second terminal units on a path through which subscribers' packet information is transmitted. In the first and second terminal units, first and second communication state control units are provided for controlling the consistency of the communication state between the two terminal units by sending/receiving communication state control information using the maintenance link.

Maintenance communication control system in an ISDN service

A packet data and a header added to a head of the packet data for specifying a transfer condition of the packet data are divided together to data blocks (DBs) each having a designated data length, consisting of an initial DB including the header and an initial part of the packet data, intermediate DBs each including an intermediate part of the packet data and a last DB including a last part of the packet data, so as to be transferred to a data transfer destination in a data processor of a switching system in accordance with write commands for the initial, intermediate and last DBs respectively, and a read command for asking whether the DBs are correctly transferred is sent to the data transfer destination once, after the DBs are transferred. When the DBs are transferred, the packet data is restored at the data transfer destination only by synthesizing the transferred DBs and removing the header.

Data transfer method performed in a data processor provided in a

In the transmission data test mode of the integrated circuit, the user sets test transmission data as transmission data and supplies a transmission data test command to a returning unit, whereby the test transmission data output from the transmission unit is returned by the returning unit and received by the reception unit. In that case, a format converting unit receives the test transmission data in the data format of the transmission data. Then, by comparing the test transmission data and data received by the reception unit, the user can carry out a transmission data test. In the reception data test mode of the integrated circuit, the user sets test reception data, designates a reception timing and supplies a reception data test command to a test reception data input unit, whereby the test reception data is received by the reception unit via the test reception data input unit. Then, by comparing the test reception data and data received by the reception unit and corresponding to the designated reception timing, the user can perform a reception data test.

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Kawasaki, Japan

Ryouzi Takano