Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Ryousuke Takizawa

Kenji Tsuchida

Yoshihisa Iwata

Tsuneo Inaba

Daisaburo Takashima

Tatsuya Kishi

Junichi Miyamoto

Naoharu Shimomura

Shinichiro Shiratake

Masahiro Takahashi

Akira Katayama

Hiroshi Ito

Yu Shimada

A memory device includes a memory cell connected between first and second signal lines, a first wiring connected to the first signal line, a second wiring connected to the second signal line, and a precharging circuit connected to the first wiring. During a write sequence, the precharging circuit charges the first signal line and the first wiring, the memory cell is activated according to a voltage difference between the first signal line and the second signal line, and a write current generated from parasitic capacitances of both the charged first signal line and the charged first wiring flows from the first wiring to the second wiring via the activated memory cell.

Memory device

A first switching element in a memory cell is configured to transition from an ON state to an OFF state in response to a voltage applied between its two terminals being decreased. A read circuit is configured to place the second interconnect in a floating state, and, after placing the second interconnect in the floating state and based on a comparison between a first voltage of the second interconnect at a time point of the first switching element becoming the OFF state and a second voltage, either apply a third voltage to the second interconnect and then place the second interconnect in the floating state, or apply a fourth voltage lower than the third voltage to the second interconnect without applying the third voltage to the second interconnect.

Memory device including memory cell including variable resistance element and switching element

According to one embodiment, a memory device includes a first wiring line, a second wiring line, a memory cell connected between the first and second wiring lines, including a resistance change memory element having first and second resistance states, and a two-terminal switching element connected in series to the resistance change memory element, and a voltage application circuit which applies a write voltage signal having a first polarity and setting a desired resistance state to the resistance change memory element, to the memory cell, and applies, after the write voltage signal is applied to the memory cell, a second polarity voltage signal having a magnitude that prevents the two-terminal switching element from being set to the on-state, to the memory cell.

Voltage applications to a memory cell including a resistance change memory element in series with a two-terminal switching element

A semiconductor memory device includes a memory cell including a switching element and a resistance change element. A first circuit supplies a constant current to the memory cell for an amount of time and a second circuit applies a constant voltage to the memory cell for an amount of time. The semiconductor memory device places the memory cell into an ON state by applying, while applying a first current to the memory cell by the first circuit, a first voltage to the memory cell by the second circuit and performs readout on the memory cell in the ON state by the first current.

Semiconductor memory device

According to one embodiment, a memory device includes first and second lines, a memory cell connected between the first and second lines, and including a resistance change memory element and a switching element, a current supply circuit supplying write current to the memory cell when data is written to the resistance change memory element, a detection circuit detecting an on state of the switching element after supply operation of the write current is enabled, and a control circuit controlling a time required until supplying the write current from the current supply circuit is stopped, wherein a starting point of the controlling the time is a time point at which the on state of the switching element is detected.

According to one embodiment, a semiconductor memory device, includes a memory cell comprising a switching element and a resistance change element; and a first circuit that applies a first voltage to the memory cell, places the memory cell into an ON state by applying a second voltage to the memory cell while applying the first voltage to the memory cell in parallel, generates a third voltage based on a resistance state of the resistance change element by performing first voltage application to perform a first readout on the memory cell in the ON state, writes first data into the memory cell.

A memory device includes a first sense amplifier, and a second sense amplifier. During a read operation, a first signal based on a first output of the first sense amplifier corresponding to data stored in a memory cell before writing reference data therein and a second signal based on a second output of the first sense amplifier corresponding to data stored in the memory cell after writing reference data therein, are supplied to the second sense amplifier, which compares the first and second signals to output a comparison result representative of the data stored in the memory cell. During a test operation, a third signal based on the first output and a fourth signal based on an output from a voltage supply circuit are supplied to the second sense amplifier, which outputs a comparison result of the third and fourth signals as a test result.

Memory device that performs a read operation and a test operation

A semiconductor memory device comprises a first memory cell with a first variable resistance element. A first write controller is configured to write data into the first memory cell using a first voltage that is supplied via a first wiring. A second write controller configured to write data into the first memory cell using a second voltage that is lower than the first voltage when the first voltage supplied via the first wiring is reduced below a threshold level.

A non-volatile semiconductor memory device that can reduce power consumption includes plural memory banks containing nonvolatile plural memory cells. A common data bus is shared by plural memory banks and transmits the data of the memory cells. The plural switches are provided respectively between the electric source and plural memory banks. A controller controls the plural switches. The controller, in the data reading-out action or the data writing-in action, makes at least one of the switches corresponding to at least one of the memory banks accessible in a conduction state, and other switches in a non-conduction state.

Semiconductor memory device and driving method of the same

According to one embodiment, nonvolatile semiconductor memory device comprises: a memory mat including a memory cell having a variable resistance element; a write driver which applies a write current to the memory cell in one of a first direction and a second direction opposite to the first direction in write; and a read driver which applies a verify read current to the memory cell in one of the first direction and the second direction in verify read after write.

Nonvolatile semiconductor memory device

A memory includes a cell array including memory cells storing data, and a write driver writing data to the cells. A write driver performs or does not perform writing of write data according to write mask data input along with the write data. A multiplexer selectively outputs a write protect signal or the write mask data. The write protect signal is fixed to a command prohibiting the write data from being written. The command is included in the write mask data. A write protect controller controls the multiplexer to output the write protect signal when an address of a write protect area in the cell array matches an address of the write data. The write protect controller controls the multiplexer to output the write mask data as it is when the address of the write protect area in the cell array does not match the address of the write data.

Semiconductor storage device and control method thereof

In one embodiment, a non-volatile memory includes a first buffer that receives notification of power-down and outputs a first signal changed from a first value to a second value based on the notification, a first controlling unit that receives and outputs a command signal, a second controlling unit that generates and outputs a basic signal that has a third value when the command signal output from the first controlling unit indicates an active command and has a fourth value when the command signal indicates a command corresponding to a write back instruction or the first signal has the second value, a memory cell array in which memory cells are arrayed, and a sense amplifier circuit that reads data from the memory cell.

Ferroelectric random access memory and memory system

A nonvolatile memory includes a memory area including plural first magnetoresistive elements each serving as a memory element, each first magnetoresistive element including a first storage layer and a first reference layer, with a first insulating film therebetween. A fuse circuit storing correction information of the memory area when a defect exists in the memory area, includes plural second magnetoresistive elements and plural fuse elements, the second magnetoresistive elements each serving as an anti-fuse element. Each second magnetoresistive element includes a second storage layer and a second reference layer, with a second insulating film therebetween. The fuse elements each store at least part of the correction information. A redundancy area includes plural third magnetoresistive elements each serving as a redundancy element, each third magnetoresistive element including a third storage layer and a third reference layer, with a third insulating film therebetween. When an external address signal matches the correction information, one third magnetoresistive element is selected.

Nonvolatile memory

According to one embodiment, a nonvolatile memory includes a memory area including a first magnetoresistive element, and a fuse circuit including a second magnetoresistive element serving as an anti-fuse element and configured to store correction information of the memory area when a defect exists in the memory area. The first magnetoresistive element includes a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer. The second magnetoresistive element includes a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer.

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Naka Kanagawa, Japan

Ryousuke Takizawa