Sandisk Technologies Inc.

Ryousuke Itou

Tatsuya Hinoue

Kengo Kajiwara

Kenzo Iizuka

Seje Takaki

Manabu Hayashi

Akihisa Sai

Tetsuya Yamada

Takuro Maede

Johann Alsmeier

Hiroyuki Ogawa

Yanli Zhang

Masanori Tsutsumi

Akio Nishida

Shinsuke Yada

Seiji Shimabukuro

Satoshi Shimizu

Ramy Nashed Bassely Said

Naohiro Hosoda

Genta Mizuno

Yusuke Yoshida

Ryoichi Honma

Yusuke Mukae

Keisuke Izumi

Akira Nakada

Masanori Terahara

Shigehiro Fujino

Yujin Terasawa

Takashi Yuda

Yusuke Oda

Hajime Kimura

Noriyuki Nagahata

A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

Three-dimensional memory device with doped semiconductor bridge structures and methods for forming the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel.

Three-dimensional NAND memory device with reduced reverse dipole effect and method for forming the same

A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. A set of one or more bridge structures including a doped semiconductor material is formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement

A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same

First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

Method for etching bottom punch-through opening in a memory film of a multi-tier three-dimensional memory device

A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.

Vertical thin film transistors with surround gates

A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.

A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Method of making a monolithic three dimensional NAND string using a select gate etch stop layer

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Yokkaichi, Japan

Ryousuke Itou