Fuji Electric Co., Ltd.

Ryouichi Kawano

Michio Nemoto

Tomoyuki Yamazaki

Mituhiro Kakefu

Hiroshi Takishita

Motoyoshi Kubouchi

Takashi Shiigi

Daisuke Ozaki

Kazuhiro Kitahara

A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.

Method of manufacturing semiconductor device

A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion provided in the semiconductor substrate and a terminating structure provided at a termination of the front surface side of the semiconductor substrate and that mitigates an electric field of the termination. In the electric field distribution of the front surface side of the terminating structure, during rated voltage application, an electric field at the end portion of the active portion side may be smaller than a maximum value of an electric field distribution of the front surface side. In addition, the electric field distribution of the terminating structure may have a maximum peak of the electric field on the edge side opposite to the active portion with respect to a center of the terminating structure.

Semiconductor device

The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an nregion, a plurality of p-guard ring regions, and a stopper region disposed away from the p-guard ring regions are provided. By providing the p-diffusion region, withdrawal of holes that concentrate to the p-anode region at the time of reverse recovery is suppressed, so that the semiconductor device has a high reverse recovery tolerance.

In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.

Growing community of inventors

Matsumoto, Japan

Ryouichi Kawano