Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Toshiba Microelectronics Corporation

Ryouhei Kirisawa

Masaru Kito

Hideaki Aochi

Yoshiaki Fukuzumi

Tomoko Fujiwara

Yoshimasa Mikajiri

Shigeto Oota

Ryota Katsumata

Masaru Kidoh

Hiroyasu Tanaka

Megumi Ishiduki

Yosuke Komori

Junya Matsunami

Riichiro Shirota

Masaki Momodomi

Fujio Masuoka

Seiichi Aritome

Yoshihisa Iwata

Tetsuo Endoh

Ryozo Nakayama

Yasuo Itoh

Kazunori Ohuchi

Tomoharu Tanaka

Satoshi Inoue

Yoshiyuki Tanaka

Hiroshi Iwahashi

Kaori Kawasaki

Takeshi Imamura

Masamichi Asano

Masahiko Chiba

Shigeyoshi Watanabe

Koichi Toita

Tetsuo Endo

Takashi Mori

Tomoo Hishida

Hideko Odaira

Naohiro Matsukawa

Toshiyuki Hayakawa

Kunihiro Yamada

Tetsuro Endoh

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Nonvolatile semiconductor memory device and method for manufacturing same

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

Nonvolatile semiconductor memory device and method for driving same

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies Vvoltage to the first wiring, applies Vvoltage lower than Vto a selected cell gate of the selected cell transistor, applies Vvoltage not higher than Vand higher than Vto a non-selected cell gate of the first memory transistors, applies Vor Vvoltage not higher than Vand not lower than Vto the first select gate, and applies Vor Vvoltage higher than Vand not higher than Vto the second wiring or sets the second wiring in a floating state.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.

Growing community of inventors

Kanagawa-ken, Japan

Ryouhei Kirisawa