Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Ryota Aburada

Toshiya Kotani

Hiromitsu Mashita

Chikaaki Kodama

Fumiharu Nakajima

Takafumi Taguchi

Taiga Uno

Katsumi Iyanagi

Masahiro Miyairi

Weiting Wang

Michiya Takimoto

A semiconductor device includes a first to a third wiring-line. The first wiring-line is provided on a first layer in a first direction. The second wiring-line is provided on the first layer in the first direction. A first side surface of the second wiring-line faces the first wiring-line. A second side surface of the second wiring-line is opposite to the first side surface. The third wiring-line is provided on the first layer in the first direction, and faces the second side surface of the second wiring-line. An end portion of the first wiring-line projects further from an end portion of the second wiring-line in the first direction. The end portion of the second wiring-line projects further from an end portion of the third wiring-line in the first direction, and curves toward the third wiring-line. Alternatively, the end portion of the second wiring-line increases in width toward its edge portion.

Semiconductor device having a wiring line with an end portion having rounded side surfaces and manufacturing method thereof

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)second sidewall film matching a pattern of a n(where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2)&#xd7;(&#x3bb;/NA) or less when an exposure wavelength of an exposure device is &#x3bb;, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

Method of fabricating semiconductor device and semiconductor device

One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.

Pattern generating method, pattern forming method, and pattern generating program

Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects

A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

Pattern dimension calculation method and computer program product

Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

Growing community of inventors

Kanagawa, Japan

Ryota Aburada