Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer System, Ltd.

Hitachi Tokyo Electronics Co., Ltd.

Akita Electronics Systems Co., Ltd.

Hitachi Microcomputer Systems Ltd.

Ryosuke Kimoto

Kunihiko Nishi

Kunihiro Tsubosaki

Ichiro Anjoh

Asao Nishimura

Hideki Tanaka

Akio Hasebe

Chuichi Miyazaki

Yukiharu Akiyama

Tomoaki Kudaishi

Masanori Shibamoto

Hiroshi Koyama

Hiroshi Kawakubo

Gen Murakami

Kazunari Suzuki

Masahiro Ichitani

Kenichi Yamamoto

Masamichi Ishihara

Ryo Haruta

Junichi Arita

Akihiko Iwaya

Michio Tanimoto

Hisao Nakamura

Seiichi Ichihara

Taisei Jin

Shunji Koike

Shiro Yamashita

Kosuke Inoue

Takamichi Suzuki

Junichi Suzuki

Tatsuya Yoneda

Masnori Shibamoto

Munehiro Yamada

Akira Nagai

Masahiko Ogino

Masahide Harada

Shuji Eguchi

Toshiaki Morita

Takafumi Nishita

Takashi Kikuchi

Takashi Miwa

Takehiro Ohnishi

Noriou Shimada

Chikako Imura

Masaru Kawakami

Yoichi Abe

A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

Semiconductor device and manufacturing method thereof

For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

Semiconductor device

Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.

Method for manufacturing semiconductor device and electronic device and method for calculating connection condition

In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 &#x3bc;m or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3&#xd7;10(Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

Semiconductor device having a particular electrode structure

The impact strength resistance of a solder joint portion of a semiconductor device is improved. The semiconductor device has a joint structure wherein a jointing layer which does not contain sulfur substantially is arranged between an underlying conductive layer and a lead-free solder layer and further between the jointing layer and the lead-free solder layer is formed an alloy layer comprising elements of these layers.

Semiconductor device with joint structure having lead-free solder layer over nickel layer

A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Method of manufacturing a ball grid array type semiconductor package

The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads are arranged on one side opposite to the side on which bonding pads (effective pins) are arranged in the semiconductor chip. Dummy leads are formed on an insulating tape The semiconductor chip is supported with inner lead portions connected to the corresponding bonding pads and the inner lead portions of the dummy leads connected to the corresponding dummy pads

Semiconductor device and process for producing the same

An aggregate of semiconductor devices, including semiconductor packages packaging the semiconductor devices, the packages being on a tape which is wound on a reel, is provided. The aggregate of semiconductor devices includes the semiconductor packages arranged consecutively on a first tape; and the aggregate also includes a second tape, which is a spacer tape, having spacers (protrusions), provided between adjacent windings of the first tape on the reel, providing spaces for the semiconductor packages. The semiconductor packages can be provided with bumps, e.g., on the side of the first tape opposite the side of the first tape having the semiconductor packages thereon, and the first tape can be a flexible printed circuit board.

Aggregate of semiconductor devices including semiconductor packages arranged on a first tape and wound on a reel and also including a spacer tape provided with spacers

Growing community of inventors

Hamura, Japan

Ryosuke Kimoto