Yazaki Corporation

Ryosuke Kawano

Satoshi Ishikawa

Kimihiro Matsuura

Hajime Okamoto

A voltage detection apparatus includes: a battery including a plurality of unit cells mutually connected in series; a plurality of blocks, each block including at least one of the plurality of unit cells; a plurality of voltage detectors, each detector connected to respective one of the blocks, and detecting a voltage between both ends of the unit cell in the one of the blocks; a plurality of reference power sources, each source connected to respective one of the voltage detectors, and at least one of the reference power sources having higher accuracy than the other reference power sources; and a correcting unit which corrects a detection result of the voltage detector which is connected to the other reference power source on the basis of a detection result of the voltage detector which is connected to the reference power source with the higher accuracy.

Voltage detection apparatus

A voltage detection apparatus includes: a battery including unit cells mutually connected in series; a first block including at least one of the unit cells; a second block including at least one of the unit cells, and provided adjacent to the first block; a first voltage detector connected to the first block, which detects a voltage between both ends of the unit cell in the first block, and which includes: a current source; a current detection element connected to the current source; and a voltage measuring unit which detects a voltage between both ends of the current detection element; and a second voltage detector connected to the second block, which has a similar construction with the first voltage detector. An abnormality detector of the voltage detection apparatus detects an abnormality of the voltage detectors in accordance with the voltages between both ends of the current detection elements.

The present invention is to provide a voltage detector having a common communication line for reducing a manufacturing cost. A low voltage line CPU transmits a detection instruction including an assignment of one address among a plurality of blocks. The detection instruction is branched by a transmitting bus line for concurrently transmitting to a plurality of voltage detector units. When one of the voltage detector units receives the detection instruction with the address being same as a self-address thereof, the voltage detector unit detects output voltages of unit cells and transmits the detected result to the low voltage line CPU. When the received address is not the self-address, the voltage detector unit does not transmit the detected result.

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Saiki, Japan

Ryosuke Kawano