Sandisk Technologies Inc.

Ryosuke Kaneko

Michiaki Sano

Akio Nishida

Mitsuteru Mushiga

Kenji Sugiura

A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, the memory films containing a charge storage layer and blocking dielectric which generally extend along the first horizontal direction and laterally undulate along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.

Three-dimensional flat NAND memory device including wavy word lines and method of making the same

A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, memory films located on a respective sidewall of the alternating stacks, generally extending along the first horizontal direction, and laterally undulating along the second horizontal direction, and a plurality of discrete vertical semiconductor channels located on a sidewall of a respective one of the memory films.

An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

Three-dimensional memory device containing a replacement buried source line and methods of making the same

A portion of a charge trapping layer adjacent to a select drain gate electrode can be removed employing a differential-rate etch process that provides an accelerated etch rate to a doped portion with respect to an undoped portion. If a silicon nitride layer is employed as the charge trapping layer, then angled ion implantation of boron atoms to an upper portion of the silicon nitride layer can increase the etch rate of the boron-doped portion of the silicon nitride layer in phosphoric acid. The charge trapping layer is etched back such that a remaining portion of the charge trapping layer can be present only at levels of control gate electrodes, and absent at each level of select drain gate electrodes. Threshold voltage shift for the select drain gate electrodes can be eliminated or reduced by removal of the charge trapping layer at each level of the select drain gate electrodes.

Growing community of inventors

Yokkaichi, Japan

Ryosuke Kaneko