Toshiba Memory Corporation

Kioxia Corporation

Ryosuke Isomura

Junichi Sato

Akio Sugahara

Noriyasu Kumazaki

Masashi Yamaoka

Norichika Asaoka

Yuzuru Shibazaki

Kazuto Uehara

Takaya Handa

Yuri Terada

Bushnaq Sanad

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Memory device which generates operation voltages in parallel with reception of an address

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

Growing community of inventors

Matsudo Chiba, Japan

Ryosuke Isomura