Kabushiki Kaisha Toshiba

Fuji Electric Co., Ltd.

Toshiba Electronic Devices & Storage Corporation

Ryosuke Iijima

Tatsuo Shimizu

Shinya Kyogoku

Johji Nishio

Takashi Shinohe

Teruyuki Ohashi

Katsuhisa Tanaka

Kazuto Takao

Chiharu Ota

Shinichi Kimoto

Shinsuke Harada

Yukio Nakabayashi

Shigeya Kimura

Yusuke Kobayashi

Hisashi Yoshida

Toshiyuki Oshima

Tomoaki Inokuchi

Tatsunori Sakano

Hiro Gangi

Shigeto Fukatsu

Keiko Ariyoshi

Kentaro Ikeda

Toshihide Ito

Shunsuke Asaba

Masahiko Kuraguchi

Masato Koyama

Hiroshi Kono

Yuichiro Mitani

Tatsuya Nishiwaki

Takeshi Watanabe

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include preparing a structure body, the structure body including a silicon carbide member and a first film stacked with the silicon carbide member. The first film includes silicon and oxygen. The method can include performing a first treatment of heat-treating the structure body in a first atmosphere including hydrogen. The method can include, after the first treatment, performing a second treatment of heat-treating the structure body in a second atmosphere including nitrogen and oxygen. An oxygen concentration in the second atmosphere is not less than 5 ppm and not more than 1000 ppm.

Semiconductor device and method for manufacturing semiconductor device

According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.

Wafer having a silicon carbide crystal layer with stacking faults provided on a silicon carbide base body and semiconductor device manufactured using the wafer

A semiconductor device of embodiments includes: a silicon carbide layer including a trench, a n-type first SiC region, a p-type second SiC region on the first SiC region, a n-type third SiC region on the second SiC region, a fourth SiC region of p-type between the first trench and the first SiC region, and a fifth SiC region electrically connecting the second SiC region and the fourth SiC region; and a gate electrode in the trench. The first trench has a first region extending in a first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. The second width of the second region in the second direction is larger than the first width of the first region in the second direction. The fifth SiC region is disposed in the second direction of the second region.

Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane parallel to a first direction and a second direction orthogonal to the first direction, and a second plane facing the first plane, the silicon carbide layer including a first trench and a second trench extending in the first direction; a gate electrode in the first trench and the second trench; a gate insulating layer; a gate wiring extending in the second direction, intersecting with the first trench and the second trench, connected to the gate electrode; a first electrode; a second electrode; and an interlayer insulating layer provided between the gate electrode and the first electrode. Neither the gate electrode nor the gate wiring is present between an end of the first trench in the first direction and the interlayer insulating layer.

Semiconductor device, inverter circuit, drive device, vehicle, and elevator

According to one embodiment, a semiconductor device includes a supporter including a first surface, first, second, and third conductive parts, a semiconductor region, and an insulating part. A first direction from the first toward second conductive part is along the first surface. The semiconductor region includes first, second, and third partial regions. A second direction from the first toward second partial region is along the first surface and crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes a counter surface facing the second conductive part. A direction from the counter surface toward the third conductive part is along the second direction. The insulating part includes an insulating region. At least a portion of the insulating region is between the counter surface and the third conductive part.

Semiconductor device

A semiconductor device of an embodiment includes: a first trench in a silicon carbide layer and extending in a first direction; a second trench and a third trench located in a second direction orthogonal to the first direction with respect to the first trench and adjacent to each other in the first direction, n type first silicon carbide region, p type second silicon carbide region on the first silicon carbide region, n type third silicon carbide region on the second silicon carbide region, p type fourth silicon carbide region between the first silicon carbide region and the second trench, and p type fifth silicon carbide region located between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode; and a second electrode. A part of the first silicon carbide region is located between the second trench and the third trench.

A semiconductor device of an embodiment includes a first trench extending in a first direction in a silicon carbide layer; a second trench and a third trench adjacent to each other in the first direction; a first silicon carbide region of n type; a second silicon carbide region of p type on the first silicon carbide region; a third silicon carbide region of n type on the second silicon carbide region; a fourth silicon carbide region of p type between the first silicon carbide region and the second trench; a fifth silicon carbide region of p type between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode, part of which is in the second trench, the first electrode contacting the first silicon carbide region between the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode.

According to one embodiment, a semiconductor device includes first, and second conductive members, first, second, and third semiconductor regions, and an insulating part. A direction from the first conductive member toward the second conductive member is along a first direction. The first semiconductor region includes first and second partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The first conductive member is between the first partial region and the second conductive member. A direction from the second partial region toward the second semiconductor region is along the first direction. A direction from the second conductive member toward the second semiconductor region is along the second direction. The third semiconductor region is between the second partial region and the second semiconductor region. The insulating part includes a first insulating region, a second insulating region, and a third insulating region.

Semiconductor device and method for manufacturing the same

A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.

A semiconductor device of an embodiment includes an element region and a termination region surrounding the element region. The element region includes a gate trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type on the first silicon carbide region, a third silicon carbide region of n-type on the second silicon carbide region, and a fourth silicon carbide region of p-type sandwiches the first silicon carbide region and the second silicon carbide region with the gate trench, the fourth silicon carbide region being deeper than the gate trench. The termination region includes a first trench surrounding the element region, and a fifth silicon carbide region of p-type between the first trench and the first silicon carbide region, the fifth silicon carbide region same or shallower than the fourth silicon carbide region. The semiconductor device includes a gate electrode, a first electrode, and a second electrode.

Semiconductor device, inverter circuit, drive device, vehicle, and elevating machine

According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.

Semiconductor device having multiple conductive parts

A semiconductor device of an embodiment includes a silicon carbide layer having first and second plane, the silicon carbide layer including trench having a first portion and a second portion, the second portion having a width smaller than the first portion, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, a p-type third silicon carbide region between the second silicon carbide region and the first plane and having a p-type impurity concentration lower than the second silicon carbide region, an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and an n-type fifth silicon carbide region between the second portion and the second silicon carbide region and having an n-type impurity concentration higher than the first silicon carbide region; and a gate electrode in the trench.

Semiconductor device, inverter circuit, driving device, vehicle, and elevator

An embodiment of a semiconductor device including a silicon carbide layer having a first and a second planes; a first silicon carbide region of first conductivity type in the silicon carbide layer; a second silicon carbide region of second conductivity type in the silicon carbide layer between the first silicon carbide region and the first plane; a third silicon carbide region of the first conductivity type in the silicon carbide layer located between the second silicon carbide region and the first plane; a first electrode located on a side of the first plane; a second electrode located on a side of the second plane; a gate electrode; an aluminum nitride layer containing an aluminum nitride crystal between the second silicon carbide region and the gate electrode; and an insulating layer between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

An embodiment is a semiconductor device includes a silicon carbide layer having a first plane and a second plane facing the first plane; a gate electrode; an aluminum nitride layer located between the silicon carbide layer and the gate electrode, the aluminum nitride layer containing an aluminum nitride crystal; a first insulating layer located between the silicon carbide layer and the aluminum nitride layer; and a second insulating layer located between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Semiconductor device, inverter circuit, driving device, vehicle, and elevator having a reduced on-resistance with a silicon carbide layer

A semiconductor device of an embodiment includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and the silicon carbide layer having a first plane and a second plane, the silicon carbide layer including a first trench, p-type first silicon carbide regions and n-type second silicon carbide regions alternately disposed, a p-type third silicon carbide region between the second silicon carbide region and the first plane, and an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and a p-type fifth silicon carbide region between the first silicon carbide region and the first trench, a gate electrode in the first trench, and a gate insulating layer. The length of the first silicon carbide region perpendicular to the first plane is longer than a depth of the first trench.

Growing community of inventors

Setagaya, Japan

Ryosuke Iijima