Nec Electronics Corporation

Ryoko Sasaki

Kenichiro Anjo

Katsumi Togawa

Masato Motomura

Taro Fujii

An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be processed including a command corresponding to the data. The input DMA circuit first transfers the command to the state management unit, and then transfers the data to be processed to the data path unit.

Stream processor and information processing apparatus

A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A stream processor for performing a plurality of processes parallel to each other on the data to be processed acquires a descriptor from the memory, reads data to be processed from the memory according to the input address information contained in the descriptor, processes the data, and stores the processed data back into the memory according to the output address information contained in the descriptor.

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Kanagawa, Japan

Ryoko Sasaki