Seiko Instruments Inc

Agency of Industrial Science and Technology

Agency of Industrial Science and Technology and Seiko Instruments Inc.

Ryoji Takada

Yoshikazu Kojima

Kenji Aoki

Yutaka Hayashi

Masaaki Kamiya

The present invention provides novel structures of MOS field effect transistor which operate with high speed and low power consumption. This has been achieved through providing epitaxial growth layers on a substrate of high impurity doping concentration in which the thickness of epitaxial growth layers is controlled with a degree of accuracy on the order of a single atom layer.

MOS field effect transistor and its manufacturing method

A method of manufacturing a MOS field effect transistor comprises forming on a semiconductor substrate a first epitaxial growth layer having an impurity doping concentration lower than that of the semiconductor substrate, forming on the first epitaxial growth layer a second epitaxial growth layer having an impurity concentration higher than that of the first epitaxial growth layer and having a thickness equal to or less than a diffusion depth of a source and a drain region, and forming on the second eptiaxial growth layer a third epitaxial growth layer having an impurity concentration lower than that of the second epitaxial growth layer and having a thickness equal to or less than that of a depletion layer at a channel region.

The semiconductor nonvolatile memory has integrated memory cells, each being operative to carry out writing and reading of information in random-access basis and having an electric charge storage structure effective to memorize the information in nonvolatile state. The information is temporarily written into each memory cell in volatile state, and thereafter the temporarily written information is written at one into the respective electric charge storage structure of each memory cell, thereby effecting quick writing of nonvolatile information into the respective memory cells of multi-bits.

Semiconductor volatile/nonvolatile memory

The memory device is comprised of a plurality of memory arrays. Firstly, one of the memory arrays is selected for operation. When the selected one reaches an operational limit due to repetition of data rewriting which causes degradation of writing performance, another memory array is then selected for subsequent operation to thereby improve performance of the semiconductor nonvolatile memory device.

Semiconductor nonvolatile memory

A nonvolatile memory has integrated memory cells each operative to carry out writing and reading of information on a random-access basis and each having an electric charge storage structure effective to memorize the information in a nonvolatile state. The information is temporarily written into each memory cell in a volatile state, and thereafter the temporarily written information is written at once into a respective electric charge storage structure of each memory cell, thereby effecting high speed writing of nonvolatile information into the respective memory cells.

Growing community of inventors

Tokyo, Japan

Ryoji Takada