Kabushiki Kaisha Toshiba

Ryoji Maruyama

Hideyuki Funaki

Hiroshi Mochizuki

Kanae Fujii

A voltage (V ) and a current (A ), input from input terminals (T ) and (T ), are A/D converted to 1-bit output data by delta modulators and 1-bit output data of the delta modulator is delayed, using a phase-shifting circuit implemented by either a RAM (semiconductor memory) or shift registers, by an amount equivalent to 90&deg; of the input voltage (V ), before a subsequent circuit performs a calculation of a reactive power. This circuit configuration reduces analog circuitry and enables a compact, low-cost implementation, even for use in an LSI.

Electric power calculation system

Power arithmetic apparatus detects a first variation amount of a voltage in proportion to a voltage of a measuring object and a second variation amount of a voltage in proportion to a current of the measuring object, and calculates power of the measuring object based on the first variation amount detected and the second variation amount detected.

Power arithmetic apparatus

First and second 1-bit A/D converters convert respective input voltages being in direct proportion to voltage and current of a measurement system into respective 1 bit codes. First and second up-down counters whose up/down count in respective clock terminals are controlled in accordance with respective 1 bit codes which are output from the first and second 1-bit A/D converters, and output A/D converted values of the respective input voltages. A latch holds data one clock prior to currently input data and outputs the data. An adder-subtractor adds and subtracts respective output data of the first and second up-down counters and a numerical value 1 to and from output data of the latch under control of respective output data of the first and second 1-bit A/D converters and an exclusive OR value of the respective output data and outputs arithmetic data which being in proportion to a product of the respective input voltages to the latch. An adder integrates the output data of the latch.

Arithmetic unit

A device for measuring an electrical quantity of a system under measurement including a Hall element equipped with a pair of current input terminals and a pair of voltage output terminals. In the Hall element, four equivalent resistances are formed. The device also includes a device for applying a magnetic field proportional to a value of a first current on the Hall element, and a current supply circuit for flowing a second current between the current input terminals. The device further includes an output circuit for detecting a first voltage appearing between the output voltage terminals and outputting the first voltage as a measured value corresponding to the electrical quantity, and an offset compensation circuit for detecting an offset appearing between the voltage output terminals for varying one of the four equivalent resistances based on the offset thus detected so as to compensate the offset. The device also includes an input resistance control circuit for varying remaining three of the equivalent resistances such that a second voltage generated between the current input terminals caused by a flow of the second current is maintained at a predetermined value. An input resistance value of the Hall element is thereby held constant.

Electrical quantity measurement device

In a Hall element, a semiconductor layer is surrounded by a first trench filled with an insulator. A first current supply portion of an n+-type semiconductor is disposed adjacent the semiconductor layer and the first trench. Second current supply portions are also disposed adjacent the semiconductor layer and the first trench and symmetrical with respect to the first current supply portion. Sensor portions of an n+-type semiconductor are disposed adjacent the semiconductor layer and the first trench at about the center between the first and second current supply portions, respectively. A magnetic flux perpendicular to the upper surface of the semiconductor layer can be detected by the foregoing arrangement.

Hall element for detecting a magnetic field perpendicular to a substrate

A power multiplication circuit including a Hall element for generating between voltage output terminals thereof a first output voltage corresponding to a power of a system under measurement. The circuit further includes a voltage polarity detection circuit for detecting a polarity of a power source voltage of the system and an operating circuit connected to receive the first output voltage and the polarity for amplifying the first output voltage and for changing over between amplified first output voltage and an inverted voltage of the amplified first output voltage to generate a second output voltage in accordance with the polarity. The circuit also includes an integrating amplifier circuit for integrating the second output voltage to generate an integrated signal and a variable resistance element connected between one of the voltage output terminals of the Hall element and ground, and connected to receive the integrated signal. The resistance thereof is changed by the integrated signal so that an offset voltage of the Hall element is reduced to zero.

Power multiplication circuit which reduces an offset voltage of a Hall

A transmission input/output device for signal transmission through a telephone line, with reduced power consumption, size, and cost. The device includes: a resistor, connected to the telephone line, for setting a signal input and output impedance; and a transmission control circuit for amplifying the transmission signals to be outputted to the telephone line, including: a variable resistor, connected in series with the resistor, for supplying voltages corresponding to the transmission signals to be outputted to the telephone line into the resistor according to changes of an impedance of the variable resistor; and an operational amplifier for controlling the changes of the impedance of the variable resistor by supplying an output according to the transmission signals to be outputted to the variable resistor.

Transmission input/output device with reduced power consumption

A multiplier having pulse width modulators for modulating input signals into pulse signals whose pulse widths are corresponding to the levels of the input signals and which are asynchronous to each other; an oscillator for outputting a pulse signal at a frequency higher than any one of those of the pulse signals from the pulse width modulators; a logical gate portion which receives the pulse signals from the pulse width modulators as well as the pulse signal from the oscillator to executes predetermined logical operation on the pulse signals; and a subtracter which calculates, according to the pulse widths of the pulse signals from the pulse width modulators, the number of pulses outputted within a predetermined interval from the oscillator to provide a signal proportional to the product of levels of the input signals.

Growing community of inventors

Kawasaki, Japan

Ryoji Maruyama