Renesas Electronics Corporation

Ryoji Ishikawa

Satoshi Shibatani

Kenta Suto

Yoshio Inoue

Ken Saito

Toshiaki Terayama

Osamu Kobayakawa

Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs.

LSI design method

In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

LSI design method and LSI design device

A power domain is automatically generated. A computer performs a function simulation processfor evaluating whether or not a designed circuit satisfies a specification, and a clustering processwhich obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

Obtaining power domain by clustering logical blocks based on activation timings

In order to improve a failure detection rate in a layout automatic design process of a DFT circuit, signal lines of the DFT circuit are aggregated by an AND tree circuitor an OR tree circuit instead of an EXOR tree circuit, and outputs thereof are received by an observation flip-flop. When a failure detection process of the DFT circuit is performed by using the EXOR tree circuit in the case where partial circuits outputting respective signal lines are shared or the partial circuits have the same structure, the signals cancel each other and the failures of the original partial circuits cannot be detected in some cases. However, such a trouble can be prevented by using the AND tree circuitor the OR tree circuit instead of the EXOR tree circuit.

Method and software for designing semiconductor integrated circuit including observation circuit for detecting circuit failure

To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

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Kanagawa, Japan

Ryoji Ishikawa