Sony Corporation

Saturn Licensing LLC

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Ryoji Ikegaya

Makiko Yamamoto

Yuji Shinohara

Takashi Yokokawa

Yasushi Fujinami

Lui Sakai

Satoshi Okada

Tatsuo Shinbashi

Nabil Sven Loghin

Kenichi Nakanishi

Ken Ishii

Naohiro Adachi

Hidetoshi Kawauchi

Keiichi Tsutsui

Naoki Yoshimochi

Yusuke Oike

Hiroyuki Yamagishi

Hiroyuki Iwaki

Seiji Kobayashi

Masanori Sato

Akira Endo

Akira Nakamura

Hiroyuki Kamata

Tomohiro Matsumoto

Akito Sekiya

Masayuki Hattori

Lachlan Bruce Michael

Daisuke Kawakami

Hiroshi Aoki

Kentaro Nakahara

Hayato Wakabayashi

Toshihiro Fujiki

Hideaki Okubo

Yasuhiro Iida

Toshiyuki Hiroi

Hiroyuki Mita

Tatsuki Amimoto

Sawako Kiriyama

Yusuke Yoneyama

Suguru Houchi

Takashi Horiguti

Kazuki Yoshiyama

Muhammad Nabil Sven Loghin

Kimiya Kato

Hideshi Motoyama

Takumi Yajima

Yutaka Nakada

A signal processing circuit outputs, in a case where a first timing at which a first input signal changes is earlier than or same as a second timing at which a second input signal changes, a first output signal at the first timing and a second output signal at the second timing, and outputs, in a case where the first timing is later than the second timing, the first output signal and the second output signal at the second timing.

Signal processing circuit, signal processing device, and signal processing method using logic circuit

In group-wise interleaving, interleaving of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed in a unit of a bit group of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code that has undergone group-wise interleaving is returned to an original arrangement. The technology can be applied to a case of transmitting data using the LDPC code. The data processing device and data processing method can ensure excellent communication quality in data transmission using an LDPC code.

Data processing device and data processing method

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes, in group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bit. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence, the present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Provided is a solid-state imaging apparatus and an electronic device, in which a scale of circuits, to perform arithmetic operation of the neural network, is suppressed. A solid-state imaging apparatus according to an aspect of the present disclosure includes a pixel array unit and a processing unit. The pixel array unit has a plurality of first pixels that generate electric signals, which have a logarithmic characteristic with respect to light quantity, as first pixel signals. The processing unit performs arithmetic processing of the first neural network based on a plurality of first input data, which are based on the plurality of first pixel signals read from the pixel array unit, and a plurality of logarithmic weighting factors which express strength of the connection between the plurality of first nodes by a logarithm.

Solid-state imaging apparatus and electronic device to perform arithmetic operation of neural network

A signal processing circuit has a plurality of first circuits each including a first-time-length-signal output circuit that outputs a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes and a second-time-length-signal output circuit that outputs the first time-length signal as a second time-length signal at timing based on a control signal. The signal processing circuit includes a second circuit that outputs the second time-length signal having the longest time length among a plurality of the second time-length signals output respectively from the plurality of first circuits.

Signal processing circuit, signal processing device, and signal processing method to suppress power consumption

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

[Problem] To provide design support useful for hardware implementation of a neural network. [Solution] Provided is an information processing device including a control unit that controls presentation of information related to an optimization structure when at least a part of a network structure of a designed neural network has been optimized for hardware processing. Provided is an information processing method including a step of controlling, by a processor, presentation of information related to an optimization structure when at least a part of a network structure of a designed neural network has been optimized for hardware processing.

Information processing device and information processing method

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

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Kanagawa, Japan

Ryoji Ikegaya