Matsushita Electric Industrial Co., Ltd.

Ryoichi Yamada

Hisashi Adachi

Shunsuke Hirano

Yasunori Miyahara

Yukio Hiraoka

Hisashi Takahashi

Hiroki Kojima

A frequency synthesizer device comprising a PLL circuit ( ) and a frequency-division ratio control circuit ( ). The PLL circuit ( ) includes a phase comparator ( ), a low-pass filter ( ), a voltage-controlled oscillator ( ), and a variable frequency divider ( ). The frequency-division ratio control circuit ( ) controls the variable frequency divider ( ) such that a frequency division ratio of the variable frequency divider ( ) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider ( ) and an output fdiv obtained via a delay element ( ) are used as clocks of an accumulator portion ( ) in the frequency-division ratio control circuit ( ). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit ( ) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.

Fractional-N frequency synthesizer with multiple clocks having different timings

A frequency synthesizer is provided with a prescaler and a counter which output a signal having a frequency generated by frequency-dividing an output signal of a VCO a reference frequency divider for frequency-dividing a frequency of a reference signal of a reference signal source a frequency adjusting meas operated in such that a frequency error between the output signal of the counter and the output signal of the reference frequency divider is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO is switched; and also a bias control means for applying an arbitrary voltage V to a control voltage terminal of the VCO so as to bring an output signal of a charge pump into a high impedance state when the frequency adjusting means is operated. Since the resonant frequency of the resonant circuit is changed in response to an actual oscillation frequency of the VCO the frequency synthesizer can be phase-locked at a desirable frequency. Also, since the VCO can be manufactured in the IC form, the compact VCO can be made in low cost.

Method and apparatus for synthesizing high-frequency signals for wireless communications

In a frequency synthesizer device in which a frequency-division ratio control circuit and other circuits are integrated on the same semiconductor substrate, a power supply for supplying a power to the frequency-division ratio control circuit is provided separately from a power supply for supplying a power to other circuits. A power supply voltage supplied from the power supply to the frequency-division ratio control circuit is set lower than a power supply voltage supplied to other circuits. The noise generated by the frequency-division ratio control circuit can be reduced by setting the power supply voltage lower, and also C/N degradation can be reduced. Since the noises can be suppressed even if the frequency is increased, a lock-up time can be reduced and the lower power consumption can be attained.

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Yokosuka, Japan

Ryoichi Yamada