Meiko Electronics Co., Ltd.

Ryoichi Shimizu

Tohru Matsumoto

Yoshio Imamura

Mitsuaki Toda

Takuya Hasegawa

Mitsuo Iwamoto

In a mark forming step in a manufacturing method for a component incorporated substrate in which an electronic component is positioned with reference to a mark formed in a copper layer, when an imaginary line extending from a search center of a search range of a sensor, to an edge side of the search range is represented as a search reference line and an imaginary line extending, in a state in which a mark center, is matched with the search center, from the mark center in the same direction as the search reference line to an outer ridgeline of the mark is represented as a mark reference line, the mark formed in a shape in which the outer ridgeline of the mark is present in a position where a length of the mark reference line is in a range of 30% or more of the search reference line.

Manufacturing method for component incorporated substrate and component incorporated substrate

The method includes positioning an electronic component using main marks formed on a metal layer and mounting the electronic component on a second surface of the metal layer with an adhesive layer interposed between the metal layer and both of the electronic component and terminals; then burying the electronic component and the main marks in an insulating substrate; then removing part of the metal layer and forming a first window for exposing the main marks therefrom and a second window for exposing the adhesive layer including a position corresponding to the terminal therefrom; then using the exposed main marks as references and forming a laser via hole LVH reaching the terminal in the adhesive layer exposed from the second window; and thereby forming a wiring pattern from the metal layer electrically connected to the terminal through a first conductive via formed by plating the LVH with copper.

Component-embedded substrate manufacturing method

A thin conductive layer which is to form a conductor pattern () is prepared, a mask layer () is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads () and a dummy solder pad () are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals () of an electric or electronic component () are connected to the actual solder pads (), an insulating base () of resin is formed which is laminated directly on or indirectly via the mask layer () on the conductive layer and in which the component () is embedded, and part of the conductive layer is removed by using the dummy solder pad () as a reference, to form the conductor pattern ().

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Ayase, Japan

Ryoichi Shimizu