Seiko Epson Corporation

Ryohei Tamura

Shuichi Tanaka

Haruki Ito

Yasuhito Aruga

Michiyoshi Takano

Tomoyuki Shindo

Hironori Ota

Kazuo Yazawa

A semiconductor chip holding tray, includes: a base substrate; a first projection provided on the front surface of the base substrate, and disposed on a short edge side of the perimeter of a holding area, has a depression; a first raised portion provided on the front surface, and is disposed on a long edge side of the perimeter; a triangular cross-section second projection provided on the rear surface of the base substrate, and is disposed on a short edge side of the perimeter of a holding area; and a second raised portion provided on the rear surface, and is disposed on a long edge side of the perimeter of the holding area. The tray is arranged such that when two trays are stacked the second projection is fitted in the depression of the first projection.

Semiconductor chip holding tray

A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.

Semiconductor device, circuit substrate, electro-optic device and electronic appliance

A semiconductor chip housing tray that is used in a state of being stacked in a plurality of stages and houses a plurality of semiconductor chips, includes: a base plate; a plurality of upper surface protruding parts provided to an upper surface of the base plate and dividing the upper surface of the base plate into a plurality of first semiconductor chip housing areas; and a plurality of under surface protruding parts provided to an under surface of the base plate and dividing the under surface of the base plate into a plurality of second semiconductor chip housing areas. In the semiconductor chip housing tray, a margin width of the first semiconductor chip housing areas with respect to the semiconductor chips is smaller than a margin width of the second semiconductor chip housing areas with respect to the semiconductor chips.

Semiconductor chip housing tray

Growing community of inventors

Chino, Japan

Ryohei Tamura