Renesas Technology Corp.

Renesas Electronics Corporation

Ryohei Higuchi

Toshiyuki Hiraki

A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.

Data processing apparatus

In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.

Data processing system

A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.

Data transfer control apparatus

Two bus masters share an external device. One particular bus master has an arrangement for issuing a data pre-read instruction, at the time of issuing a data read request. Upon reception of the data read request accompanying with the data pre-read instruction issued by the particular bus master, an external device controller instructs an external address generator to continuously generate an address for performing normal readout this time, and an address for the next pre-read, and executes readout by the next pre-read address, provided that when the normal readout this time is finished, the bus master has not issued a data read request. The normal data read based on the normal readout address this time is held in a data holder, and the pre-read data read based on the next pre-read address is stored in a pre-read data storage.

Data transfer control circuit in system LSI

An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a write command to the SDRAMwhen a request is made to access the SDRAM, without deactivating the accessed row, until a detection signal that detects the last column is asserted. The SDRAM access control section deactivates the accessed row when the detection signal is asserted.

Access controller that efficiently accesses synchronous semiconductor memory device

DMA transfer request signals corresponding to respective channels are received and held in respective transfer request holding circuits. DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lower priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.

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Tokyo, Japan

Ryohei Higuchi