Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Ryogo Yanagisawa

Tadahiro Yoshida

Shinichi Hashimoto

Toru Iwata

Masazumi Yamada

Satoshi Takahashi

Hiroyuki Iitsuka

Yoshiki Kuno

Toshiaki Tsuji

Hirotoshi Uehara

Shoichi Gotoh

Norihiko Mizobata

Shuji Kato

Shoichi Goto

Hirokazu Sugimoto

Isamu Ishimura

Syuji Kato

Kiyotaka Iwamoto

Hiroyuki Iltsuka

Eiichi Moriyama

Shinya Murakami

Manabu Kawabata

An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Video input device and video display system

A digital signal receiver comprises a signal separating section (), a clock signal generating section (), a video data processing section (), an audio data processing section (), and a control section (). The clock signal generating section () generates an operation clock signal () for the signal separating section (), the video data processing section (), and the audio data processing section (). The control section () pauses the signal separating section (), the video data processing section (), and the audio data processing section () until receiving a clock stability signal () indicating that the operation clock signal () is stable, the clock stability signal () being generated by the clock signal generating section ().

Digital signal receiver and method for controlling the same

An authentication processing apparatus includes an authentication unit, having a circuit that performs authentication phases included in processing for authenticating an external device. A command holding unit holds a first command that indicates whether or not each of the authentication phases is performed by the authentication unit. An authentication controller causes the authentication unit to perform an authentication phase that is indicated, by the first command, to be performed by the authentication unit. A CPU performs software processing of an authentication phase that is indicated, by the first command, not to be performed by the authentication unit.

Authentication processing apparatus and authentication processing method

A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method

A semiconductor integrated circuit (D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit () produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit () has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section () converts the parallel data signal, which has been converted by a scaler (), to the serial data signal in synchronism with the fourth clock signal. A frequency divider () produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector () selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Semiconductor integrated circuit and transmitter apparatus having the same

A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Video signal processor capable of suppressing excessive heat generation, method using the same, display device and method using the same

A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising:

Multichannel display data generating apparatus, medium, and informational set

A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

Data detector and multi-channel data detector

In a transmitting section for a video signal transmitting/receiving system for transmitting digital video signals using a plurality of transmission channels, video guard band signals are inserted into video signals associated with the transmission channels immediately before transition from a blanking region to an effective video region. In a receiving section for the system, the inserted video guard band signals are detected for the respective transmission channels. A skew among the transmission channels is detected based on the detection result. To synchronize the video guard band signals among all the transmission channels, with reference to one of the video signals associated with a transmission channel with the longest delay (i.e., delayed by one clock cycleT), a delay ofT is given to the other video signals. As a result, even if a skew occurs among the transmission channels, correct pixel data is displayed.

Video signal transmitting/receiving system

A multichannel display data generating apparatus displays AV data on a plurality of screens. A channel displayed on one of the screens is displayed without a program clock reference.

Display apparatus displaying certain data without a program clock reference

A data transmitter for detecting a reference time stamp for use in reproducing a system clock from a transport packet data of a first transport stream, adding the detected reference time stamp as a header information to the transport packet data, converting the transport packet data and the header information into a second transport stream, and transmitting the second transport stream.

Data transmitter and data receiver

A wipe waveform signal generating apparatus includes a wipe width generator generating a wipe width. A wipe waveform extended width holding device outputs a horizontal extended width and a vertical extended width. A wipe waveform calculator receives the wipe width, the horizontal extended width, and the vertical extended width, and outputs a rectangular-area horizontal width, a rectangular-area vertical width, a rectangular-area horizontal starting position, and a rectangular-area vertical starting position. A change signal generator receives the rectangular-area horizontal width, the rectangular-area vertical width, the rectangular-area horizontal starting position, and the rectangular-area vertical starting position, and outputs a wipe waveform signal.

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Osaka, Japan

Ryogo Yanagisawa