Sony Corporation

Mitsubishi Electric Corporation

Kabushiki Kaisha Toshiba

Toshiba Energy Systems & Solutions Corporation

Ryo Yamamoto

Yohei Fukuma

Toru Karashima

Yoshihiro Ogawa

Daisuke Ishii

Yujin Morisawa

Naoya Okada

Kenichi Agata

Nozomi Ozaki

Noriyuki Minegishi

Hisaya Miyashita

Naohiko Otake

Takashi Hasegawa

Keita Hibi

Takuya Motoishi

Masaaki Kato

Yuki Kubota

Masaaki Kaneko

Kazuhiro Ishida

Junichi Kanai

Keishi Tsuchiya

Hideki Nakamura

Hirotaka Yamamoto

Masaharu Asano

Tatsuaki Sato

Kazushi Sakuma

Masahiro Takihara

Hirofumi Okabe

Akinori Yamada

Yuichi Shoji

Koki Murano

Fumitoshi Karube

Yosuke Kiyama

Chiaki Namiki

Kanae Kawauchi

Fumi Takahashi

Hidetomo Iwagawa

Takuya Goda

Tatsuya Tsuzuki

Keijiro Yasumura

Yoshiko Haruguchi

A reception unit () receives NN information () and non-functional requirements () demanded for a circuit. A search unit () generates combinations of interlayer architectures and intra-layer architectures as architecture combinations (). Then, the search unit () searches for a plurality of architecture combination candidates () that reduce an amount of delay as the non-functional requirements, from among the architecture combinations (). A determination unit () determines whether each of the plurality of architecture combination candidates () satisfies the non-functional requirements () or not. A candidate information generation unit () generates candidate information () including architecture candidates () that satisfy the non-functional requirements among the plurality of architecture combination candidates ().

Architecture estimation device, architecture estimation method, and computer readable medium

This geopolymer molding production method comprises: a mixing step (S1) for mixing a first material containing aluminum and silicon with a hydrate of an alkali stimulant containing a hydrate of an alkaline hydroxide and/or a hydrate of an alkaline silicate; a compaction step (S2) for compacting the mixture obtained in the mixing step (S1) into a compacted mixture; and a curing step (S3) for curing the compacted mixture.

Geopolymer molding production method and geopolymer molding production system

A software studying unit () calculates software processing time of each of a plurality of functions in a target source program. A data-flow graph generation unit () generates an inter-function data-flow graph of the plurality of functions based on the target source program. A hardware studying unit () calculates hardware processing time of each function and a circuit scale of each function by a high-level synthesis for the target source program. An implementation combination selection unit () selects, based on the software processing time of each function, the hardware processing time of each function, the circuit scale of each function, and the inter-function data-flow graph, an implementation combination of one or more functions to be implemented by software and one or more functions to be implemented by hardware.

Support system and computer readable medium

It is desirable to provide a technology for enabling to make a reply to a received message by simple operation. There is provided an information processing device including an output control unit that, in a case where a received message has been obtained through a communication unit, controls display of first and second candidates of a transmission message, and sets the first candidate as a candidate in a selected state, in which: in a case where first pressing force has been detected by a first pressure sensor, the output control unit switches the candidate in the selected state from the first candidate to the second candidate; and in a case where second pressing force has been detected by a second pressure sensor, the output control unit controls the communication unit in such a manner that the candidate in the selected state is transmitted as the transmission message.

Information processing device, information processing method, and program

A high-level synthesis device executes high-level synthesis on a behavioral description including a plurality of loop descriptions and a logical description. An extraction unit extracts loop descriptions that can be merged with the logical description without changing a function, as loop description candidates, from the plurality of loop descriptions. The extraction unit also calculates characteristics of a circuit of a case where the logical description is merged with each of the loop description candidates, as circuit characteristics. A determination unit determines a loop description to be merged with the logical description, from the loop description candidates based on the circuit characteristics. A merge unit merges the logical description with the loop description determined by the determination unit.

High-level synthesis device, high-level synthesis method, and computer readable medium

A structure determination unit () obtains an operational description () and determines a candidate of a circuit structure applicable to a plurality of execution units as a structure candidate, the operational description () describing an operation of a circuit and including the plurality of execution units. A decision unit () calculates, as a circuit characteristic (), a characteristic of the circuit when the circuit structure of the plurality of execution units is the structure candidate and outputs the structure candidate as a determined circuit structure () when the circuit characteristic () meets a threshold (). A high level synthesis unit () performs high level synthesis on the operational description () so that the circuit structure of the plurality of execution units becomes the determined circuit structure ().

High level synthesis apparatus, high level synthesis method, and computer readable medium

A binding data acquiring unit acquires binding data describing a plurality of memory modules as functional modules of a design target circuit. A memory module selecting unit selects an external memory module to be implemented as an external memory outside of the design target circuit from the memory modules described in the binding data on the basis of a constraint condition on the design target circuit.

Circuit design support apparatus, circuit design support method, and computer readable medium

A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.

Architecture generating device

A scheduling result file () indicates that one or more processes are assigned to each of a plurality of process steps to be executed sequentially. A target specification section () specifies a target process that is a process performing computation and an identical-type process that is a process assigned to a process step executed after a process step to which the target process has been assigned and performing computation which is identical in type to the target process among processes in the scheduling result file. A destination specification section () specifies, as a destination step, a process step that enables a computing unit to be shared between the target process and the identical-type process when the target process is assigned. A scheduling change section () changes description of the scheduling result file to description in a state in which the target process has been assigned to the destination step.

Circuit design support apparatus and computer readable medium

Provided is an external structure configured to be attached to or detached from an electronic device having a concave portion formed on a surface of a housing, and a connection connector provided in a position of the concave portion receding from the surface of the housing, the concave portion having a cross-sectional shape enabling locking of the external structure, the external structure including a first fitting unit configured to be fitted to the connection connector.

Electronic device and external structure configured to attach to or detach from the electronic device

Keyboard

A latency adjusting part calculates a necessary delay based on the number of FFs that are required to be inserted between respective modules through high level synthesis of a behavioral description. An input FF stage number acquiring part extracts a pin having an input that receives an FF, and acquires the number of stages of input FFs of FF reception. A latency re-adjusting part obtains an optimum delay based on the above-mentioned necessary delay and input delay. A former-stage module analyzing part detects, based on the above-mentioned synthetic log or HDL, a state having a minimum total number of FFs. An FF insertion optimizing synthesis part subjects an entire circuit to high level synthesis again based on the above-mentioned optimum delay and an FF inserting position obtained based on the state having the minimum number of FFs, to thereby obtain optimized HDL.

Semiconductor integrated circuit design supporting apparatus, method, and program

A processing part inputs a behavior description code in which a write access array to be accessed to write and a read access array to be accessed to read are used. The processing part analyzes the behavior description code, and determines an order of using each write access address and an order of using each read access address when the behavior description code is executed. Further, the processing part performs either one of a write access order changing process to change the order of using the write access addresses when the behavior description code is executed based on the order of using the read access addresses and a read access order changing process to change the order of using the read access addresses when the behavior description code is executed based on the order of using the write access addresses.

Circuit design support device, circuit design support method and program

Electrical connector

Growing community of inventors

Tokyo, Japan

Ryo Yamamoto