Fujitsu Semiconductor Limited

Fujitsu Corporation

Ryo Tanabe

Hirofumi Watatani

Shigeo Satoh

Sadahiro Kishii

Masanori Terahara

Kaina Suzuki

The semiconductor memory device includes a memory cell, a pair of bit lines and a cell power line connected to the memory cell, a first switch connected to the bit lines and a power voltage line, a second switch connected to the cell power line and a write assist cell power line, and a write control circuit configured to control the bit lines, the first switch and the second switch, wherein the write control circuit applies a first voltage of a high level to one bit line and a second voltage of a low level to the other bit line, connects one bit line to the power voltage line and disconnects the other bit line from the power voltage line by the first switch, and then connects the cell power line to the write assist cell power line lower which is than the first voltage by the second switch.

Semiconductor memory device and method of writing into semiconductor memory device

In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved.

Manufacturing method of semiconductor device having N-channel MOS transistor, P-channel MOS transistor and expanding or contracting film

Semiconductor device having an n-channel MOS transistor, a p-channel MOS transistor and a contracting film

A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

Method of manufacturing semiconductor device having device characteristics improved by straining surface of active region

Each of channel regionsandis covered by a gate electrodevia a gate insulation filmand side wall spacersfrom its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structureon both side faces along the x-direction of each of the channel regionsand(in a non-contact state), thereby preventing stress in a z-direction from being applied by the STI element isolation structureto each of the channel regionand

Method of manufacturing semiconductor device

A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

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Kawasaki, Japan

Ryo Tanabe