Fujitsu Corporation

Ryo Takajitsuko

Yoshiharu Kato

Kiyofumi Mitsuze

Hidetoshi Iwasa

Shiro Uriu

Kenichi Okabe

Hiroya Kawasaki

Kiyohumi Mitsuze

Kenji Mitsuhashi

A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.

Communications apparatus and congestion control method

A dual apparatus having a first unit and a second unit of a same configuration, one being operated in an active state while the other in a standby state. Each of these first and second units comprises a first selector for setting a current unit to the active state if a predetermined fault occurs in the other unit; a second selector for sending information indicative of the setting of the current unit to the active state, if a predetermined fault occurs in the other unit and the first selector selects a first act state, to the other unit and, setting the current unit to the standby state, if the predetermined fault does not take place in the other unit and the first selector selects the active state and a state indicated by information supplied from the other unit is the active state; and a register for holding one of the active and standby states selected by the second selector.

Active/standby dual apparatus and highway interface circuit for interfacing clock from highway

A duplex memory control apparatus having a first control unit containing a first memory and a second control unit containing second memory, a first control unit and a second control unit connected to each other through a bus. The first control unit having a central processing unit writing write data in the first memory; a transmitter obtaining the write data to be written in the first memory by the central processing unit, a transmitter, when a write data can be specified based on another write data previously obtained, transmitting specific data smaller than a write data to the second control unit instead of the write data; a first bus mutually connecting the central processing unit, the first memory an the transmitter; a first direct memory access unit reading the write data held int eh first memory through the first but; a second bus connected with a first direct memory access unit; and an access limiter connected to the first bus and the second bus and limiting to use the first bus by the first direct memory access unit when the central processing unit uses the first bus. The second control unit having a data producing section receiving the specific data from the transmitter and producing an original write data based on the specific data; and a second direct memory access unit writing the original write data produced by the data producing section into the second memory.

Duplex memory control apparatus

An exchange equipment using STM able to achieve an improvement of an efficiency of use and an improvement of ease of increase of terminal cards, that is, an STM type exchange, including a time switch, for performing exchange processing of time division multiplexed data, wherein a ring highway is connected via a terminal common unit to an upstream highway and a downstream highway coupled to this time switch via a highway interface unit or directly and wherein a plurality of terminal cards are connected to this ring highway. Each terminal card is provided with an add/drop unit which drops and adds the data from and to an assigned time slot on the ring highway according to control information indicating time slot assignment information determined by the control unit and adds the data and with a card control unit which controls the add/drop unit.

Growing community of inventors

Kawasaki, Japan

Ryo Takajitsuko