Toshiba Memory Corporation

Ryo Sekiguchi

Yasuhiko Kurosawa

Shingo Yanagawa

Eriko Akaihata

A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n&#x2265;3). The first circuit is configured to calculate an estimated value of each of n&#x2212;m determination voltages based on values of m determination voltages (2&#x2264;m&#x2264;n&#x2212;1) among the n determination voltages, and calculate a difference between a value of each of the n&#x2212;m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n&#x2212;m determination voltages.

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Tokyo, Japan

Ryo Sekiguchi