Hitachi Maxell, Limited

Hitachi, Ltd.

Elpida Memory, Inc.

Other

Subaru Corporation

Globeride, Inc.

Nec Corporation

Nitto-denko Corporation

Nec Electronics Corporation

Ryo Nagai

Satoru Yamada

Norikatsu Takaura

Kiyonori Oyu

Riichiro Takemura

Hiroyuki Uchiyama

Hideyuki Matsuoka

Kousuke Okuyama

Teruhisa Ichise

Hiroshi Kujirai

Takahiro Kumauchi

Hisao Asakura

Kazuhiro Hata

Tomonori Sekiguchi

Shinichiro Kimura

Masayuki Nakamura

Hiroshi Fukunaga

Masafumi Miyamoto

Isamu Asano

Yoshitaka Tadaki

Toshihiro Sekiguchi

Tetsuichi Kudo

Hidehito Obayashi

Akira Gotoh

Kozo Kajita

Jinbao Zhao

Katsuya Masaki

Ryoichi Nakamura

Hiroshi Kashino

Daito Tanimoto

Yasuo Arishima

Shinsuke Shibata

Gun Seki

Hitoshi Watanabe

Tatsuya Ishii

Yoshitaka Nakamura

Yoshio Sakai

Tsugio Takahashi

Hideo Nakamura

Hideo Fujiwara

Shinichi Miyatake

Koichi Seki

Kouki Noguchi

Masao Abe

Shoji Saibara

Masato Isogai

Akira Kawakami

Masashi Suenaga

Hiroyuki Higuchi

Tsunemi Ohiwa

Osamu Saito

Kiyoshi Sato

Hisamitsu Kamezaki

Hideki Nishihama

Shouji Mochizuki

Shoichiro Tateishi

Tsuyuki Suzuki

Noboru Odani

Shuichi Yamamoto

Hiroshi Hattori

Shigetomi Michimata

Masahiko Takai

Kazumi Yoshimitu

Shoko Ibuki

Masuhiro Onishi

Masahiro Hyoma

Shinichiro Iuchi

Toshio Ohshima

Masanobu Kizu

Kiyoaki Shakushiro

A vehicle includes a filter, a negative-pressure mechanism, and a first opening and closing mechanism. The filter is disposed in an exhaust passage coupled to an engine. The negative-pressure mechanism is configured to pressurize a portion of the exhaust passage upstream of the filter to a negative pressure less than an atmospheric pressure. The first opening and closing mechanism includes an opening disposed in the exhaust passage, and a valve configured to selectively open and close the opening. The valve is configured to, when the exhaust passage becomes negatively pressurized by the negative-pressure mechanism, open the opening.

Vehicle

Fishing reel

A method for manufacturing a catalyst includes depositing a catalyst slurry containing at least a catalyst metal and water on a support, depositing particles of a water-absorbing polymer on a surface of the catalyst slurry, expanding the particles to a predetermined size with the water present in the catalyst slurry, and firing the support having the catalyst slurry and the particles deposited on the catalyst slurry.

Method for manufacturing catalyst and catalyst

Reel body of fishing reel

A liquid fuel cell comprising a plurality of unit fuel cells each having a positive electrode () for reducing oxygen, a negative electrode () for oxidizing liquid fuel, and an electrolyte layer () interposed between the positive electrode () and the negative electrode (), and a section () for storing liquid fuel (), wherein power can be generated stably while reducing the size by arranging the plurality of unit fuel cells on the substantially same plane. Each electrolyte layer of the unit fuel cell preferably constitutes a continuous integrated electrolyte layer.

Liquid fuel cell with a planer electrolyte layer

A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implanting phosphorous into the silicon layer, diffusing at least the phosphorous by heat-treating the silicon layer, and patterning the silicon layer by using a dry etching technique.

Semiconductor device having silicon layer in a gate electrode

Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Method for manufacturing semiconductor integrated circuit device

A CMOS device includes a silicon substrate, a gate insulating film, and a gate electrode including a silicon layer doped with boron and phosphorous, a tungsten nitride layer and a tungsten layer. A ratio of a maximum boron concentration to a minimum boron concentration in a boron concentration profile across the thickness of the silicon layer is not higher than 100. The CMOS device has a lower NBTI (Negative Bias Temperature Instability) degradation.

Semiconductor device having a silicon layer in a gate electrode

A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a pdiffused region; implanting indium into the surface of the pdiffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

Semiconductor device and method of manufacturing the same

Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Hybrid semiconductor device having an n+ (p) doped n-type gate and method of producing the same

An air-hydrogen battery with high energy density and satisfactory cycle characteristics is provided. The air-hydrogen battery includes: a positive electrode made of an air electrode; a negative electrode provided with a hydrogen-absorbing alloy; and a cation-exchange film or an anion-exchange film formed as an electrolyte between the positive electrode and the negative electrode, wherein a periphery of the hydrogen-absorbing alloy of the negative electrode is covered with an anion-exchange resin, whereby the contact area between the anion-exchange resin that functions as an electrolyte and the hydrogen-absorbing alloy is increased, and the utilization factor and resistance to corrosion of the hydrogen-absorbing alloy are enhanced.

Air-hydrogen battery

A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

Integrated circuit device with P-type gate memory cell having pedestal contact plug and peripheral circuit

Growing community of inventors

Tokyo, Japan

Ryo Nagai