Fuji Xerox Co., Ltd.

Ryo Kukimiya

Kazuo Yamada

Junichi Uchiyama

Masahiro Ishiwata

Mitsuyuki Tamatani

Junichi Okuyama

Masatomo Igarashi

Hirofumi Sasaki

A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.

Reconfigurable logical circuit

A data processing apparatus includes a circuit selecting unit and a decoding processor. The circuit selecting unit selects a decoder circuit for each data part of encoded target data. The decoder circuit is suitable for an arrangement of run lengths in the data part. The decoding processor performs reconfiguration to form the decoder circuit selected for the data part, and decodes the target data.

Data processing apparatus, data processing method, and non-transitory computer readable medium

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Kanagawa, Japan

Ryo Kukimiya