Analog Devices,inc.

Intel Corporation

Other

Ryo Inoue

Ravi P Singh

Gregory A Overkamp

Charles P Roth

Michael J Allen

William C Anderson

Juan Guillermo Revilla

Ravi Kolagotla

Raghavan Sudhakar

Tim Landreth

In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.

Peak power reduction when updating future file

In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

Hardware loops and pipeline system using advanced generation of loop parameters

In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.

Use of a future file for data address calculations in a pipelined processor

In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.

Method and apparatus for restoring registers after cancelling a multi-cycle instruction

In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I&plus;M<B, a second corrected target module address when I&plus;M>&equals;B&plus;L and an uncorrected module address when B<&equals;I&plus;M<B&plus;L.

Modulo addressing

In one embodiment, a programmable processor is adapted to conditionally move data between a pointer register and a data register in response to a single machine instruction. The processor has a plurality of pipelines. In response to the machine instruction, a control unit directs the pipelines to forward the data across the pipelines in order to move the data between the registers.

Register move operations

Methods and apparatus are provided for transferring data words from a source to a destination. The apparatus includes a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.

Growing community of inventors

Austin, TX, United States of America

Ryo Inoue