Kabushiki Kaisha Toshiba

Ryo Haga

Shinji Miyano

Tomoaki Yabe

Takeshi Nagai

Kenji Numata

Tohru Furuyama

Osamu Wada

Katsuhiko Sato

Toshimasa Namekawa

Atsushi Nakayama

Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the fuse data is long, there is a possibility that a value of the fuse data may be inverted due to an influence of noises. Thus, a decoder is arranged in the transfer path of the fuse data, and encoded data is stored in the fuse elements. By performing error detection/correction in the decoder, the high reliability is assured with respect to chip operations and the like.

Semiconductor integrated circuit

Setting method of chip initial state

A sense amplifier is connected to a pair of bit lines to read/write data. A bit line equalizer equalizes the potentials of the pair of bit lines. A sense amplifier equalizer equalizes the potentials of two power supply nodes of the sense amplifier. The sense amplifier equalizer is constituted by two types of MOS transistors whose gate oxide films have different thicknesses. MOS transistors of one type are formed in a thick film type Tr area. MOS transistors of the other type are formed in a thick film type Tr area.

Semiconductor memory with sense amplifier equalizer having transistors with gate oxide films of different thicknesses

A semiconductor device includes a prime memory cell array, a redundant memory cell array, a holding circuit, a group of access lines, and first and second controlling circuits. The prime memory cell array includes prime memory cells. The redundant memory cell array includes redundant memory cells. The holding circuit holds an address of a defective memory cell. The access lines are respectively connected to the redundant memory cells. The first controlling circuit supplies a substitution command to substitute a redundant memory cell for the defective memory cell corresponding to the address held in the holding circuit, through the group of access lines to the defective memory cell. The second controlling circuit, when a plurality of portions of the holding circuit holds the address of the defective memory cell, disables all but one of the plurality of portions which hold the address of the defective memory cell.

Semiconductor device having a redundant memory cell and method for recovering the same

A semiconductor device includes first, second and third semiconductor circuits. The first semiconductor circuit has a first function. The second semiconductor circuit has a second function different from the first function. The third semiconductor circuit is provided in the second semiconductor circuit and has part of the first function. The third semiconductor circuit transmits/receives no signals to/from the second semiconductor circuit and operates independently of the second semiconductor circuit.

Semiconductor device having a function block provided in a macro and operating independently of the macro and method for designing the same

A semiconductor memory device comprises a data line shifting circuit for connecting a plurality of data lines and spare data lines to a plurality of I/O data lines, a plurality of I/O numbering circuits for assigning the I/O data lines shift indicating numbers as locational information, the shift indicating numbers incrementing by one for each start point for data line shifting executed by the data line shifting circuit, a selection circuit for storing the correlationship between defective column addresses and the shift indicating numbers and outputting a selection signal corresponding to the shift indicating numbers when a defective-column address is input, a shift control circuit for comparing the selection signal with the shift indicating numbers and outputting a shift control signal to the data line shifting circuit based on a result of the comparison, and a number setting selecting circuit for selectively using a plurality of I/O numbering circuits.

Semiconductor memory device having replacing defective columns with redundant columns

On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

Semiconductor integrated circuit device and its manufacturing method

A semiconductor memory device comprises: a memory cell array having memory cells arranged in the form of a matrix; a redundant column cell array configured to relieve a defective column of the memory cell array; a decoder circuit configured to decode an address to select a memory cell in the memory cell array; a plurality of data lines, to which data read out from the memory cell array or data to be written in the memory cell array, corresponding to a plurality of columns, is transferred by the decoder circuit; a data line, to which data read out from the redundant column cell array or data to be written in the redundant column cell array is transferred; a data line shift circuit configured to shift, one by one, data line and the spare data line, which are arranged on one side of a data line serving as a starting point, to which data of a defective column is to be transferred when the defective column is accessed, to connect the data line and the spare data lines to data input/output lines; a selecting circuit configured to store a correspondence between the address of the defective column and a shift point, which is assigned to each of the data input/output lines so as to increase by 1 of every starting point of the data line shift by the data line shift circuit, and configured to output a selecting signal corresponding to the shift point when the address of the defective column is inputted; and a shift control circuit configured to output a shift control signal to the data line shift circuit by comparing the selecting signal, which is outputted from the selecting circuit, with the shift point.

Semiconductor memory device and signal line shifting method

Column select lines for selecting a column in a memory cell array are provided near the memory cell array. Main column select sections including drivers are connected to one end of the column select lines. Latch circuits are connected to the other end of the column select lines. Receiving the output signal from the driver, the latch circuit, together with the driver, drives the column select line.

Semiconductor memory device which activates column lines at high speed

A semiconductor integrated circuit device has memory cell arrays capable of using shared sense amplifiers, wherein memory can be increased by refresh units to a desired capacity. Specific memory cell arrays can be selected when writing/reading and refreshing by switching address signals when writing/reading and when refreshing. The number of word lines selected when refreshing is always uniform in the memory system.

Semiconductor integrated circuit device for changing DRAM row addresses

There is disclosed a memory cell array including regular and redundant memory cells, a plurality of bit lines connected to the regular memory cells, a plurality of redundant bit lines connected to the redundant memory cells, a regular data line commonly coupled to the plurality of regular bit lines, and a redundant data line commonly coupled to the plurality of redundant bit lines. Column selection lines include regular column selection lines for selecting regular bit lines, and redundant column selection lines for selecting redundant bit lines. Furthermore, the number of redundant column selection lines is smaller than that of the regular column selection lines.

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Yokohama, Japan

Ryo Haga