Ricoh Company, Ltd.

Ryo Fukui

Tatsuya Fujii

Kazuo Sakamoto

Masafumi Tanaka

Yutaka Sato

Naoto Shiraishi

Yukihiro Imai

Yoshiteru Yamada

Makoto Matsushima

An image processing apparatus includes: a first transforming device for transforming encoded data into discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of m.times.n pixels; and a setting device for setting the values of M and N defining the size of a matrix forming each processing block used in inverse discrete cosine transform. The image processing apparatus also includes a data preparing circuit for adding discrete cosine transform coefficient data to, or deleting discrete cosine transform coefficient data from, a high-frequency domain of the discrete cosine transform coefficient data and segmented into processing blocks, each block being formed of a matrix of m.times.n pixels, and for preparing discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of M.times.N pixels; a second transforming device for subjecting the discrete cosine transform coefficient data prepared by the data preparing circuit to inverse discrete cosine transform, so that image data can be output; and an outputting device for outputting image data output from the second transforming device and segmented into processing blocks as continuous image data.

Apparatus for converting encoded data into image data, including data

An orthogonal transformation processor has a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation and inputting an output of the memory device thereto; and an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with a switching operation of writing and reading operations of the memory device. Instead of this address generator, the orthogonal transformation processor may have an address generator for designating an address of the memory device and replacing row and column addresses with each other i n accordance with calculating operations of the first and second one-dimensional orthogonal transformation calculators. The orthogonal transformation processor may further have a reading-writing control section for reading one data of the memory device and writing new results calculated by the first one-dimensional orthogonal transformation calculator to the same address after the data reading operation.

Orthogonal transformation processor for compressing information

A circuit for detecting digital data has a data-changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1; an asynchronous detecting circuit for judging whether or not the changing point is caused at a timing synchronized with the timing of the internal clock signal; an asynchronous counter for counting the number of asynchronizations; a synchronous signal generating counter for generating a synchronous signal by the internal clock signal; and a reset control circuit for controlling the timing of a reset operation of the synchronous signal generating counter in accordance with outputs of the data-changing point detecting circuit and the asynchronous counter. Another digital data detecting circuit and a method for detecting digital data are also shown.

Digital data detecting and synchronizing circuit

An image data processing apparatus includes a plurality of registers each of which outputs an output signal in accordance with a corresponding signal of a plurality of input coincidence signals derived from the input image data, the output signal indicating whether or not a corresponding register has a maximum count value, and each input coincidence signal indicating whether or not a corresponding pixel among neighborhood pixels of a target pixel of the input image data coincides with a corresponding dot among predetermined reference dots at given locations relative to the location of the target pixel in the input image data, and a state checking part for outputting a state signal indicating whether or not the output signal level of a first register having the maximum count value currently changes from the previous level by detecting the current output signal level of the first register in accordance with the input coincidence signals and in accordance with the output signals of the registers.

Image data processing apparatus for locating pixel having maximum

An orthogonal transformation processor has a first one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation; a memory device for temporarily storing an output of the first one-dimensional orthogonal transformation calculator; a second one-dimensional orthogonal transformation calculator for calculating a one-dimensional orthogonal transformation and inputting an output of the memory device thereto; and an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with a switching operation of writing and reading operations of the memory device. Instead of this address generator, the orthogonal transformation processor may have an address generator for designating an address of the memory device and replacing row and column addresses with each other in accordance with calculating operations of the first and second one-dimensional orthogonal transformation calculators. The orthogonal transformation processor may further have a reading-writing control section for reading one data of the memory device and writing new results calculated by the first one-dimensional orthogonal transformation calculator to the same address after the data reading operation.

A probability estimation table reading apparatus includes a memory part for storing a probability estimation table, the table defining, for each address value, a switch data value, a probability estimate data value, an LPS data value indicative of a next address when a more probable symbol occurs and an MPS data value indicative of a next address when a less probable symbol occurs, and a control part for reading out each the LPS data value and MPS data value for a current address value of the stored table, so that next address values required by an arithmetic coder to perform arithmetic coding data compression, can be generated. Each of the LPS data value in the stored table stored in the memory part has been replaced by the difference between a current address value and a next address value indicated by a standard LPS data value for the current address value, and each of the MPS data value has been replaced by the difference between the current address value and a next address value indicated by a standard MPS data value for the current address value.

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Yao, Japan

Ryo Fukui