Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hitachi-High-Technologies Corporation

Canon Inc.

Hitachi Microcomputer System, Ltd.

Ryo Fujita

Yasushi Fukunaga

Kazuyoshi Koga

Koyo Katsura

Takehiko Nishida

Mitsuru Soga

Takao Watanabe

Kazumasa Yanagisawa

Hitoshi Tanaka

Kazushige Ayukawa

Katsunori Suzuki

Kazuhisa Takami

Yuichi Abe

Norifumi Yanai

Takeshi Kato

Masaharu Kubo

Kouki Noguchi

Yasuhiko Takahashi

Michihiro Mishima

Isao Yasuda

Toshiyuki Kuwana

Kazunori Oniki

Osamu Kubo

Hideki Fujii

Ryoichi Inada

Masato Muraki

Haruo Yoda

Koji Ozawa

Takuma Nishimura

Kimiaki Ando

Hideyuki Hara

Yuji Inoue

Toru Sakaibara

Takaharu Morishige

Hiromichi Yamada

Yasuhiro Nakatsuka

Soshiro Kuzunuki

Teppei Hirotsu

Koji Matsuda

Kotaro Shimamura

Masahiro Shiraishi

Masataka Nishi

Dai Fujii

Yuzuru Takahashi

Shoji Nakamura

Haruyuki Nakayama

A storage device includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a free block management table, and a worn block management table. If the number of free blocks is equal to or larger than a threshold value 1, and errors of the number of equal to or larger than a threshold value 2 but smaller than a threshold value 3 are included in the data read from the nonvolatile memory, the memory controller registers the block in the worn block management table as a worn block. If the number of free blocks becomes smaller than the threshold value 1, the memory controller registers the worn block registered in the worn block management table in the free block management table as the free block.

Memory management method, storage device, and computer with the same

Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (), physical blocks are classified into three types: scratch blocks (), data blocks (), and erased blocks (). Data writing from a host device () is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

Storage device and memory controller

A storage device includes a non-volatile memory, a cache memory and a memory controller. The non-volatile memory stores a logical-to-physical address translation table for managing partitioned data and storage locations thereof. The cache memory stores a data cache and a logical-to-physical address translation table cache which holds a portion of the logical-to-physical address translation table. When the memory controller receives a data read-out request from outside, in the case no empty entry is found in the data cache, among the partitioned data in the data cache, it creates an empty entry to read out the data thereto by evacuating partitioned data of which entries in the logical-to-physical address translation table exist in the logical-to-physical address translation table cache into the non-volatile memory prior to other partitioned data.

Cache evictions from data cache based on content of address translation table cache and address translation table

High-contrast exposure is performed by use of a small dose of electron beams, a pattern is formed on a wafer with high accuracy, and high-precision inspection is performed. In pattern formation, proximity effect correction processing is performed. Moreover, exposure of electron beams is performed based on a result of filtering using an inverse characteristic of exposure characteristics of the electron beams. Furthermore, in pattern inspection, electron beams are irradiated based on a result of filtering for obtaining a peripheral region of an edge of the pattern formed.

Electron beam apparatus and method of generating an electron beam irradiation pattern

A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.

Graphic processing apparatus and method

An electronic circuit device has a high-density mount board (), on which are disposed a microcomputer () and random access memory () which are connected to each other through an exclusive memory bus () for high-speed data transfer, a programmable device () which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory () which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Electronic circuit device

An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

Graphics processor and system for determining colors of the vertices of a figure

A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

Logic compound method and logic compound apparatus

A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

Semiconductor IC device having a memory and a logic circuit implemented with a single chip

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Hitachi, Japan

Ryo Fujita