Renesas Electronics Corporation

Synaptics Display Devices Gk

Ryo Endo

Toshiya Uozumi

Keisuke Ueda

Tomomitsu Kitamura

Jiro Shimbo

Mitsunori Takanashi

A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

CDR circuit and semiconductor device

To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

High-frequency signal processing device and wireless communication system

A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.

Semiconductor device, radio communication terminal, and method for controlling semiconductor device

A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Semiconductor device

The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

ADPLL circuit, semiconductor device, and portable information device

A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.

Growing community of inventors

Kanagawa, Japan

Ryo Endo