Link a Media Devices Corporation

Skhynix Inc.

Broadlogic Network Technologies Inc.

Ryan Yu

Marcus Marrow

Haitao Xia

Shih-Ming Shih

Kai Keung Chan

Ananthanarayanan Nagarajan

Xianfeng Rui

Fan Yang

Vladimir Radionov

Ka Wing Cheung

Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request.

Programmable protocol independent bar memory for SSD controller

Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.

High performance host queue monitor for PCIE SSD controller

A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

Preamble acquisition without second order timing loops

Timing acquisition is performed. A first portion of a preamble having an end is sampled. A first phase value is determined based on the sampled first portion. A second portion of the preamble is sampled and a second phase value is determined based on the sampled second portion. An end phase value is extrapolated based at least in part the first phase value and the second phase value. A clock is adjusted using the extrapolated end phase value.

A digital automatic gain control circuit is disclosed. The circuit includes a selector, a scaler, a detector, a gain adjustor and a controller. In one exemplary aspect, the selector receives an input signal having two components, namely, the in-phase (I) and quadrature (Q) components, in digital form. The selector then selects a subset of bits from each component based on a control signal provided by the controller. The two subsets are then forwarded to the scaler. The scaler then multiplies the two subsets respectively against a gain value to generate two multiplication results. A portion of each multiplication result is then provided as output by the scaler. The gain value and the subset selection are periodically adjusted in response to the scaler output. The adjustments with respect to the gain value and the subset selection are effectuated collectively by the detector, the gain adjustor and the controller.

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Sunnyvale, CA, United States of America

Ryan Yu