Globalfoundries U.S. Inc.

Globalfoundries Inc.

Ryan W Sporer

George Robert Mulfinger

Yusheng Bian

Judson Robert Holt

Peter Baars

Rick J Carter

Hans-Jürgen Thees

Jan Höntschel

Jagar Singh

Alexander M Derrickson

Timothy James McArdle

Jeremy Austin Wahl

Alexander Lee Martin

Takako Hirokawa

Julien Frougier

Jiehui Shu

Katherina E Babich

Rohit Pal

Karen A Nummy

Manjunatha Govinda Prabhu

Kenneth John Giewont

Daniel J Jaeger

David C Pritchard

Edmund Kenneth Banghart

Keith Donegan

Hongru Ren

Dina H Triyoso

Chung Foong Tan

Amy L Child

Thomas Houghton

IC chips for photonics applications are disclosed. An example IC chip includes a substrate, an optical component above the substrate, and a first connection level above the substrate. The first connection level includes the optical component and a first cladding structure, in which the optical component is covered by the first cladding structure. The IC chip also includes a second connection level on the first connection level. The second connection level includes a first interlayer dielectric material. The IC chip further includes a second cladding structure directly above the optical component. The second cladding structure has at least a section within the second connection level. The second cladding structure is on the first cladding structure. The second cladding structure is laterally adjacent to and in direct contact with the first interlayer dielectric material. The second cladding structure includes a material different from the first interlayer dielectric material.

Cladding structure in the back end of line of photonics chips

A structure or PIC structure includes a hybrid plasmonic (HP) waveguide. The HP waveguide includes a waveguide core, and a metal silicide layer contacting the waveguide core. The metal silicide layer replaces noble metals typically provided in hybrid plasmonic waveguides, providing improved optical signal containment characteristics. The metal silicide layer is also compatible with CMOS fabrication techniques, and capable of additional scaling with other CMOS structures. The HP waveguide also has a reduce form factor compared to conventional HP waveguides, providing room for more waveguides closer together.

Structure including hybrid plasmonic waveguide using metal silicide layer

Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor

Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Structure and method for random code generation

Structures including an optical component, such as an edge coupler, and methods of fabricating a structure that includes an optical component, such as an edge coupler. The structure includes a substrate having a sealed cavity, an optical component, and a dielectric layer between the optical component and the sealed cavity. The optical component is positioned vertically over the substrate and the dielectric layer, and the optical component overlaps with the sealed cavity in the substrate.

Optical components undercut by a sealed cavity

An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

Well tap for an integrated circuit product and methods of forming such a well tap

A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

Structure with different stress-inducing isolation dielectrics for different polarity FETs

Structures and methods implement an enlarged waveguide. The structure may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a semiconductor substrate. An inter-level dielectric (ILD) layer is over the SOI substrate. A first waveguide has a lower surface extending at least partially into the buried insulator layer, which allows vertical enlargement of the waveguide, without increasing the thickness of the ILD layer or increasing the length of interconnects to other devices. The enlarged waveguide may include nitride, and can be implemented with other conventional silicon and nitride waveguides.

Enlarged waveguide for photonic integrated circuit without impacting interconnect layers

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.

Asymmetrical lateral heterojunction bipolar transistors

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

Lateral heterojunction bipolar transistors with asymmetric junctions

A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.

Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

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Mechanicville, NY, United States of America

Ryan W Sporer