International Business Machines Corporation

Ryan T Freese

Yuen H Chan

Antonio R Pelella

Arthur D Tuminaro

Uma Srinivasan

Jatinder K Wadhwa

A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a 'local bit select' circuit.

Global bit select circuit interface with dual read and write bit line pairs

Global bit select circuit with dual read and write bit line pairs

A programmable delay circuit that delays the Cclock signal by a variable amount that allows the output from the Llatch to be captured even when there is a large delta between the Llatch and its Llatch. This allows the Csignal to be adjusted within the system dependent upon the amount of cycle steal is needed. The Cclock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed Cis controlled to maintain a constant Cduty cycle.

Split L2 latch with glitch free programmable delay

A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Global bit line restore timing scheme and circuit

A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

A domino SRAM is provided with active pull-up PFET devices that overwhelm 'slow to write but very fast to read' cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional 'bit select' clamp to actively control the &#x201c;local select&#x201d; through &#x201c;wired-or&#x201d; PFET pull-up transistors. Separate read and write global &#x201c;bit line&#x201d; pairs allow the read and write performance to be optimized independently.

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Poughkeepsie, NY, United States of America

Ryan T Freese