Hrl Laboratories, LLC

Ryan T Freeman

Geoffrey P McKnight

Andrew C Keefe

Alexander R Gurga

Deborah J Kirby

Ryan G Quarfoth

David W Shahan

Geoffrey P Mcknight

A method of forming a curved semiconductor includes: forming a device layer on a semiconductor substrate; forming a metal layer on the device layer; removing the semiconductor substrate from the device layer; and curving the device layer and the metal layer.

Curved semiconductor and method of forming the same

A method of manufacturing a hybrid focal-plane array includes: forming a read-out integrated circuit with integral bending slit; forming a detector die separately from the read-out integrated circuit and including a detector with integral bending slit; and joining the read-out integrated circuit and the detector die to each other such that the read-out bending slit and the detector bending slit are aligned with each other.

Hybrid focal-plane array and method of manufacturing the same

A system configured to provide thermal regulation and vibration isolation to one or more electronic components. The system includes a sensor chassis defining an interior chamber, an electronics housing in the interior chamber of the sensor chassis, a thermoelectric cooler coupled between the sensor chassis and the electronics housing, a thermal strap coupled to the sensor chassis, and at least one isolator coupled to the sensor chassis. The system may also include an insulating material, such as Aerogel, in the interior chamber of the sensor chassis and extending around the electronics housing.

Thermal regulation and vibration isolation system

A method of manufacturing a curved semiconductor die includes: designing a semiconductor die design by conducting finite element analysis of an initial semiconductor die design having a partial spherical curvature, the initial semiconductor die design including a shape of a semiconductor die and a location and shape of a slit in the semiconductor die; when a size of a gap at the slit in the curved semiconductor die is outside a tolerance, modifying the initial semiconductor die design to provide a revised semiconductor die design and conducting another finite element analysis thereof; when the size of the gap at the slit in the curved semiconductor die is within the tolerance, manufacturing a microfabrication mask utilizing the initial semiconductor die design or the revised semiconductor die design having the size of the gap within the tolerance; forming a semiconductor die by utilizing the microfabrication mask; and curving the semiconductor die.

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Novato, CA, United States of America

Ryan T Freeman