Microsoft Technology Licensing, LLC

Ryan Scott Haraden

Adam James Muff

Miguel Comparan

Jeffrey Powers Bradford

Tolga Ozguner

Gene Leung

Christopher Michael Babecki

Matthew Ray Tubbs

Robert Allen Shearer

Christopher Jon Johnson

Shankar S Narayan

Jingyang Xue

Anasuya Vishwas Kulkarni

Ishan Jitendra Bhatt

Ashish Gupta

Michael Kersh

Rob Shearer

One example provides, on a scanning mirror display system, a method for communicating timing information for light samples that are scanned to form a displayed image. The method comprises, for a line of light samples, encoding timing information for a first light sample of the line of light samples using a first, greater number of bits to form encoded timing information for the first light sample. The method further comprises encoding timing information for a subsequent light sample of the line of light samples by computing a derivative based upon a timing of the subsequent light sample compared to a prior light sample, encoding the derivative using a second, lesser number of bits to form encoded timing information for the subsequent light sample, and sending the information for the first light sample and the subsequent light sample across the communications channel.

Derivative-based encoding for scanning mirror timing

Improved techniques for recovering from an error condition without requiring a re-transmittal of data across a high-speed data link and for improved power usage are disclosed herein. A data stream is initiated. This stream includes different types of packets. Error correcting code (ECC) is selectively imposed on a control data type packet. A transmitter node and a receiver node are connected via a hard link that has multiple virtual channels. Each virtual channel is associated with a corresponding power-consuming node. When the receiver node receives the control data type packet, error correction is performed if needed without re-transmittal. When a final data type packet is transmitted for each virtual channel, the transmitter node transmits an end condition type packet. A corresponding power-consuming node that corresponds to the respective virtual channel transitions from an active state to a low power state.

Error recovery and power management between nodes of an interconnection network

Each processor of the SIMD array performs the computations for a respective neuron of a neural network. As part of this computation, each processor of the SIMD array multiplies an input to a weight and accumulates the result for its assigned neuron each (MAC) instruction cycle. A table in a first memory is used to store which input is fed to each processor of the SIMD array. A crossbar is used to route a specific input to each processor each MAC cycle. A second memory is used to provide the appropriate weight to each processor that corresponds the input being routed to that processor.

Neural network processor

An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.

Highspeed/low power symbol compare

A method for mitigating interference across analog signal lines includes receiving a digital data stream including a plurality of discrete signal patterns configured to drive a plurality of different analog signal lines. An edge buffer for each analog signal line is populated with edge data representing pulse edges of upcoming signal patterns set to drive the analog signal line. A target buffer for a target signal line is populated with target data representing a target signal pattern. Based at least in part on determining that edge buffers corresponding to one or more potentially interfering analog signal lines include edge data corresponding to post-target pulse edges, one or more potentially interfering signal patterns are identified. A selected set of the potentially interfering signal patterns are used to modify the target signal pattern to perform preemptive interference mitigation.

Interference mitigation based on selected signal patterns

A method for mitigating interference across analog signal lines includes receiving a digital data stream including a plurality of discrete signal patterns configured to drive a plurality of different analog signal lines. An edge buffer for each analog signal line is populated with edge data representing pulse edges of upcoming signal patterns set to drive the analog signal line. A target buffer for a target signal line is populated with target data representing a target signal pattern. Edge buffers corresponding to potentially interfering analog signal lines are searched to identify potentially interfering pulse edges. A set of potentially interfering pulse edges are selected for interference mitigation, and the target signal pattern is modified to perform preemptive interference mitigation based at least in part on the selected pulse edges.

Analog signal line interference mitigation

Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.

No miss cache structure for real-time image transformations with multiple LSR processing engines

This document relates to power consumption of computing devices. One example is a face detection circuit that includes a camera interface, a processing component, and a power management interface. The camera interface can be configured to communicate with a camera. The processing component can be configured to instruct the camera to provide image data at multiple levels of resolution, and perform multiple stages of analysis on the image data obtained from the camera to detect the presence of a face in the image data. The power management interface can be configured to output an indication when the face is detected in the image data.

Face detection circuit

Optimizations are provided for late stage reprojection processing for a multi-layered scene. A multi-layered scene is generated. Late stage reprojection processing is applied to a first layer and different late stage reprojection processing is applied to a second layer. The late stage reprojection processing that is applied to the second layer includes one or more transformations that are applied to the second layer. After the late stage reprojection processing on the various layers is complete, a unified layer is created by compositing the layers together. Then, the render the unified layer is rendered.

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Duvall, WA, United States of America

Ryan Scott Haraden