International Business Machines Corporation

Ryan Michael Kruse

David S Wolpert

Brian G Veraa

Christopher J Gonzalez

Ethan E Cruz

Arden Lot Moore

Michael Wayne Harper

Terence B Hook

Leon Jacob Sigal

Matthew S Angyal

Richard Andre Wachnik

Richard Edward Serton

Zhou Jin Dong

Brian Veraa

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.

Effective metal density screens for hierarchical design rule checking (DRC) analysis

Aspects of the invention include configuring an initial tile with a plurality of portions, placing the initial tile at a location of the integrated circuit, and overlaying a clock mesh placement at the location. One or more of the plurality of portions of the initial tile that overlap with the clock mesh placement are determined, and the initial tile is modified, based on the determining the one or more of the plurality of portions, to generate a final tile. A design of the integrated circuit is finalized for fabrication based on using the final tile at the location, the final tile representing a plate of a metal insulator metal capacitor (MIMCAP).

Integrated circuit development using adaptive tile design approach for metal insulator metal capacitor insertion

Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Latch-up avoidance for sea-of-gates

A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.

Avoiding electrostatic discharge events from cross-hierarchy tie nets

An anti-counterfeiting technique presents, to a test thermoreflective mark at a first temperature, a first electromagnetic wave. A first test reflective profile for the test thermoreflective mark associated with the first temperature is recorded. A second electromagnetic wave is presented to the test thermoreflective mark at a second temperature. A second test reflective profile for the test thermoreflective mark associated with the second temperature is recorded. The first test reflective profile is compared with a first control reflective profile that is associated with a genuine thermoreflective mark. The second test reflective profile is compared with a second control reflective profile that is associated with the genuine thermoreflective mark.

Anti-counterfeiting opto-thermal watermark for electronics

Some embodiments of the inventive subject matter include a computer program product for validating a test thermoreflective mark. The computer program product can include computer usable program code configured to control a temperature regulation unit configured to govern a temperature of a thermoreflective mark. The computer usable program code can be further configured to control an electromagnetic waver emitter to present at a first temperature, a first electromagnetic wave. The computer usable program code can be further configured to record a first reflective profile. The computer usable program code can be further configured to control the electromagnetic wave emitter to present at a second temperature, a second electromagnetic wave. The computer usable program code can be further configured to record a second reflective profile. The computer usable code can be further configured to validate the thermoreflective mark based on the first reflective profile and the second reflective profile.

Growing community of inventors

Williamson, TX, United States of America

Ryan Michael Kruse