Hewlett-packard Development Company, L.p.

Ryan Lee Akkerman

Tyler J Johnson

John A Benavides

Richard W Adkisson

Harvey Ray

The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predetermined value to obtain a result. The control circuit is further configured to control a read issue rate of the first buffer based on the result. The memory is configured to store at least one of the first buffer value, the result, the read issue rate, and the TAG.

Method to improve operating performance of a computing device

One disclosed embodiment may comprise a system that includes a qualification system that qualifies data on an associated bus for capture and provides a qualification signal as a function of at least one signal that describes a characteristic of the data on the associated bus. A data capture system stores qualified data from the associated bus based on the qualification signal and a trigger signal, the trigger signal defining a capture session.

System and method to qualify data capture

A system includes a monitoring system that provides at least one signal as a function of at least some data provided on a bus. A measure of performance for the at least some data is adjusted based on the at least one signal. An analysis system is operative to perform logic analysis of the data on the bus as a function of the at least one signal.

System and method for data analysis

A programmable sync pulse generator and sync pulse generation method are operable in a clock synchronizer to effectuate data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. A phase detection circuitry is operable to sample the first clock signal with the second clock signal to determine coincident edges of the first and second clock signals. Validation circuitry is operable to validate the coincident edges based upon skew tolerance between the first and second clock signals and to generate a valid edge signal responsive thereto. Sync generation circuitry, responsive to the valid edge signal, is operable to generate synchronization pulses in the first clock domain and synchronization pulses in the second clock domain.

Programmable sync pulse generator

One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least one condition relative to input data. The at least one condition is defined by condition data that is associated with the current state. The state machine circuit associates next state data with the at least one condition based on the current state of the state machine circuit. A control circuit provides a trigger signal in response to the current state of the state machine circuit transitioning to at least one predefined state of the plurality of states.

System and method for generating a trigger signal

One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store cycles relative to an event to define the set of data, the number of store cycles varying based on the store signal.

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Allen, TX, United States of America

Ryan Lee Akkerman