Agilent Technologies, Inc.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Ryan Korzyniowski

Troy Horst Frerichs

Manuel Salcido

Victoria Meier

Michelle Marie Gentry

A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.

High-speed receiver assembly

A clock driver placement system and method are provided to place clock drivers in a standard cell block. In accordance with one aspect of the invention, a system is provided for placing clock drivers in a standard cell block. The system operates using logic that establishes an initial clock driver placement pattern, and logic that determines a number of clock drivers needed in the standard cell block to comply with a time specification. The system also includes a logic that adds clock drivers to the standard cell block using the initial clock driver placement pattern. In accordance with another aspect of the invention, a method establishes an initial clock driver placement pattern and determines a number of clock drivers needed in the standard cell block to comply with a time specification. Then, the clock drivers are added to the standard cell block using the initial clock driver placement pattern.

System and method for placing clock drivers in a standard cell block

An electrical rules checker system and method provides for correcting charge collector violations in a netlist. In accordance with one aspect of the invention, the electrical rules checker system includes a charge collector violation correction mechanism that includes a logic for analyzing the circuit configuration in a netlist, and a logic for identifying a charge collector violation in the circuit configuration. The charge collector violation correction mechanism further includes a logic for adding a charge collector diode to the netlist to correct the charge collector violation in the circuit configuration. In accordance with another aspect of the invention, a method analyzes the circuit configuration in a netlist, and identifies a charge collector violation in the circuit configuration. A charge collector diode is then added to the netlist to correct the charge collector violation in the circuit configuration.

System and method for correcting charge collector violations

A clock buffer placement system and method are provided for the placement of clock buffers in a datapath stack. In accordance with one aspect of the invention, the system positions at least one track beside the datapath stack in a netlist, and identifies placement of clock buffers needed in the at least one track. Then, the system modifies the netlist by connecting at least one datapath macro to the clock buffers on the at least one track. In accordance with another aspect of the invention, a method includes positioning at least one track beside the datapath stack in a netlist, and identifying placement of clock buffers needed in the at least one track. Then, the netlist is modified by connecting at least one datapath macro to the clock buffers on the at least one track.

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Fort Collins, CO, United States of America

Ryan Korzyniowski