International Business Machines Corporation

Qualcomm Incorporated

Ryan Joseph Pennington

Michael Stephen Floyd

Robert Walter Berry, Jr

Hugh Shen

Kenneth Lee Wright

Joab Daniel Henderson

Jarom Pena

Catherine Sherry

Walter R Lockwood

Kevin Franklin Reick

David Dean Sanner

Divya Kumar

Harmony L Prince

Daniel Campbell

Certain aspects of the present disclosure provide a method for processing data with an enhanced memory module comprising a compute core, including: receiving data at the enhanced memory module from a host processing system; storing the data in host processing system-addressable memory; transferring the data from the host processing system-addressable memory to compute core-addressable memory; processing the data with the compute core on the enhanced memory module to generate processed data; transferring the processed data from the compute core-addressable memory to the host processing system-addressable memory; and providing the processed data to the host processing system via the host processing system-addressable memory.

Inference in memory

An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

Dual in line memory module (DIMM) connector

An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.

Processor noise mitigation using differential crictical path monitoring

Processor noise mitigation using differential critical path monitoring

A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.

Non-disruptive hardware change

A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

Method for cache correction using functional tests translated to fuse repair

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Austin, TX, United States of America

Ryan Joseph Pennington