Advanced Micro Devices Corporation

Samsung Electronics Co., Ltd.

Ryan J Hensley

Brian W Amick

Joseph Kidd

Shawn Searles

Gerald Robert Talbot

James Raymond Magro

Warren Anderson

Philip Enrique Madrid

Guhan Krishnan

James David Dundas

Tahsin Askar

Milam Paraschou

Edoardo Prete

Eric C Quinnell

Hanwoo Cho

Madhu Saravana Sibi Govindan

Paul Edward Kitchin

Nicholas Humphries

Ronald L Pettyjohn

Gurunath Dollin

Fuzhou Zou

Monika Tkaczyk

Ken Yu Lim

Edward Wade Thoenes

Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.

Periodic receiver clock data recovery with dynamic data edge

According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

Micro-operation cache using predictive allocation

A system and a method are disclosed to process instructions in an execution unit (EU) that includes an operand cache (OC). The OC stores a copy of at least one frequently used operand stored in a physical register file (PRF). The EU may process instructions using operands obtained from the PRF or from the OC. In the first mode, an OC renaming unit (OC-REN) indicates to the EU to process instructions using operands obtained from the OC if processing the instructions using operands obtained from the OC uses less power than using operands obtained from the PRF. In the second mode, the OC-REN indicates to the EU to process the instructions using operands obtained from the PRF if processing the instructions using operands obtained from the PRF uses less power than using operands obtained from the OC.

Register renaming of a shareable instruction operand cache

A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

Memory diagnostics system and method with hardware-based read/write patterns

A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Method and apparatus of alternating service modes of an SOI process circuit

A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

Method and apparatus for phase selection acceleration

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Austin, TX, United States of America

Ryan J Hensley