Micron Technology Incorporated

Ryan G Fisher

Terry M Grunzke

Koji Sakui

Yasushi Matsuyama

Reshmi Basu

Daniel R Loughmiller

Cory M Steinmetz

Rahul Mitchell Jairaj

Arvin Daniel A Daguro

Noel Marquez

Kenneth Koenig

Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

Managing data integrity using a change in a number of data errors and an amount of time in which the change occurred

A method includes performing a first operation to program data to a group of memory cells of a memory device, wherein the data comprises host data and a bit pattern indicative of a first temperature of the group of memory cells and receiving a signal to perform a second operation to read the host data from the group of memory cells. The method further includes determining, responsive to receipt of the signal, whether a second temperature of the group of memory cells is outside a threshold temperature differential that is based on the bit pattern indicative of the first temperature of the group of memory cells, applying a voltage offset signal to the group of memory cells responsive to a determination that the second temperature of the group of memory cells is outside the threshold temperature differential, and performing the second operation to read the host data from the group of memory cells subsequent to application of the voltage offset signal to the group of memory cells.

Temperature differential-based voltage offset control

A method includes transferring data out of a first buffer coupled to a first plane of a plurality of planes of a memory component, where the data was previously transferred from the first plane to the first buffer responsive to an access request to sense data stored in the plurality of planes of the memory component. The method further includes transferring, subsequent to transferring the data out of the first buffer and independently of a command from a processing device, data out of a second buffer coupled to a second plane of the plurality of planes of the memory component, where the data transferred out of the second buffer was previously transferred from the second plane to the second buffer responsive to the access request.

Multi-plane switching of non-volatile memory

Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation

Various embodiments described herein provide for a memory device that can service a high priority read request during data input without losing the data inputted to the memory device prior to the high priority read request, without re-requesting data from a host, and while leaving one or more internal resources of a memory sub-system available for use by an error correction function of the memory sub-system.

Servicing memory high priority read requests

A memory sub-system comprises a number of memory components and a processing device configured to move data stored in the number of memory components based, at least partially, on a stress profile corresponding to the number of memory components.

Data storage organization based on one or more stresses

Methods for local self-boost of a selected memory cell channel, memory devices, and systems are disclosed. One such method generates a cut-off channel under each of a plurality of memory cells on one of either a source side or a drain side of a selected memory cell.

Local self-boost using a plurality of cut-off cells on a single side of a string of memory cells

The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T.

Growing community of inventors

Boise, ID, United States of America

Ryan G Fisher