Altera Corporation

Other

Ryan Fung

Vaughn Betz

David Lewis

Valavan Manohararajah

Ketan Padalia

David Galloway

Andy Louie Lee

Mark Bourgeault

David Neto

Jeffrey Christopher Chromczak

Gary Lai

Joshua David Fender

Gabriel Quan

Scott James Brissenden

Junaid Asim Khan

William Chow

David Karchmer

Navid Azizi

Michael Chan

Marcel A LeBlanc

Andy T Nguyen

Gordon Raymond Chiu

Ramanand Venkata

Ketan H Zaveri

Vadim Gouterman

Ivan Blunno

Kalen Brunham

Ling Yu

Changsong Zhang

Adrian Ludwin

Christine Lau

Kimberley Anne Bozman

A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the design by reading the computer-readable list of the physical optimizations and applying the subset to a computer-readable description of the second version of the design.

Method and apparatus for performing fast incremental physical design optimization

Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

Methods for memory interface calibration

A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second, and third netlists. Incremental placement and routing are performed on portions of the hybrid netlist that are new to the first compilation.

An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Apparatus for source-synchronous information transfer and associated methods

A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.

Method and apparatus for performing efficient incremental compilation

A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Integrated circuit device configuration methods adapted to account for retiming

An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

Metastability-hardened synchronization circuit

A method for performing timing analysis on calibrated paths includes performing static timing analysis on the calibrated paths to obtain delay and margin information. The delay and margin information are utilized to emulate operations performed during calibration.

Method and apparatus for performing timing analysis on calibrated paths

A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

Apparatus and methods for optimization of integrated circuits

A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.

Apparatus and associated methods for parallelizing clustering and placement

An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Clocking for pipelined routing

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Ryan Fung