Advanced Micro Devices Corporation

Legerity, Inc.

Ryan E Feemster

Larry David Hewitt

Brett B Stewart

Dale E Gulick

Paul G Schnizlein

Alfredo R Linz

David N Suggs

Carlin D Cabler

Glen W Brown

David E Norris

Geoffrey E Brehmer

Michael E Spak

Jeffrey M Blumenthal

Martin P Soques

Michael Hogan

David J Guercio

Alan T Torok

Miki Z Moyal

David Ray Dettmer

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

An interrupt vector approach for a processor system loads an interrupt vector directly into an address. register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

Interrupt vector method and apparatus for loading a slot memory address

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

A device and method for providing inter-processor communication in a multi-processor architecture. A post office RAM has a plurality of mailboxes. Each mailbox is write-accessible by one port, but is read-accessible by the other ports. Thus, a processor device on a port has write-access to one mailbox, but can read the other mailboxes in the post office. A transmitting processor communicates with a receiving processor, by utilizing the post office. The transmitting processor writes information into its own mailbox, and signals a receiving processor. The receiving processor determines which of the processor devices signalled it, and reads the information in the transmitting processor's mailbox.

Device and method for interprocessor communication using mailboxes owned

An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

Interrupt vector method and apparatus

A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

Charge dissipation in capacitively loaded ports

An apparatus is disclosed for comparing a first input signal with a second input signal and generating an output signal representative of that comparison in response to a system clock signal. The apparatus comprises a plurality of amplifying circuits. A first amplifying circuit generates a pair of first amplifier signals representative of the input signals applied to the apparatus. A second amplifying circuit receives the pair of first amplifier signals and generates a pair of second amplifier signals representative of the pair of first amplifier signals. A delay circuit receives the system clock signal and generates a delayed clock signal which follows the system clock signal by predetermined interval. A first switching circuit is operatively connected across the first amplifier outputs and responds to the system clock signal. A second switching circuit is operatively connected across the second amplifier outputs and is responsive to the delayed clock signal. The predetermined interval between the system clock signal and the delayed clock signal is preferably appropriate to facilitate substantial decay of noise introduced into the pair of first amplifier signals by the opening of the first switching circuit.

Comparator circuit

There is disclosed a synchronizing circuit for synchronizing a first clock signal to a second clock signal. The synchronizing circuit includes an edge-triggered set-reset latch and a delay circuit. A subclock generator generates first and second subclock signals from a synchronizing clock to control the delay circuit so that the synchronized signal at the output of the circuit is exactly one full cycle period of the synchronizing clock signal.

Growing community of inventors

Austin, TX, United States of America

Ryan E Feemster