Hewlett-packard Development Company, L.P.

Ryan Clarence Thompson

John Warren Maly

Zachary Steven Smith

Adam Caison Brown

A computer implemented method of verifying events generated by an agent includes detecting an input signal at an input of the agent, generating an expected output signal based at least in part on the input signal, detecting an output signal at an output of the agent, wherein the output signal is a translation of the input signal generated by the agent, and comparing the output signal with the expected output signal to verify whether the agent produced the output signal correctly based on the input signal.

Expectation based event verification

In one embodiment, a system and method for identifying incomplete transactions includes identifying termination of a test case run on a processor verification system, examining a pending transaction list to identify incomplete transactions, and examining at least one forward progress vector to identify incomplete transactions.

Systems and methods for identifying incomplete transactions

Disclosed are systems and methods for identifying erroneous transactions. In one embodiment, a system and a method pertain to monitoring an interface, determining information related to termination of a test case, and after the test case has terminated, identifying an incomplete transaction that should have completed prior to termination of the test case.

Systems and methods for identifying erroneous transactions

A system is provided for terminating processes that are executing on a plurality of distributed computing nodes. The system comprises a batch queuing system configured to receive jobs from a user and to dispatch jobs to the distributed computing nodes. A process shutdown interface is included that is configured to receive task criteria for terminating processes corresponding to the task criteria on the distributed computing nodes. An automatic process shutdown module is in communication with the process shutdown interface. The automatic process shutdown module is configured to retrieve information based on the task criteria from the batch queuing system regarding the processing location of jobs submitted to the batch queuing system. The automatic process shutdown module is also configured to terminate the processes on the computing nodes for jobs that are identified using the information obtained from the batch queuing system.

System and method for terminating processes in a distributed computing system

In one embodiment, a system and method pertain to identifying an output signal having indeterminate timing, creating an expectation for a signal change associated with the output signal, and adding the expectation to an ordered list of expectations for the output signal. In another embodiment, a system and method pertain to detecting a signal change, identifying a vector associated with the signal in which the change occurred, examining pending expectations of the vector until a mature expectation is identified, comparing an expected value contained in the mature expectation with the detected signal change, and reporting an error if the expected value does not match the detected signal change.

Systems and methods for conducting future signal checks

A method for identifying predictable data sharing locations includes generating a testcase thread of code, creating a list of data lines used by the generated testcase thread of code, and generating a list of predictable data sharing locations based on the data line list.

Method and apparatus for biased identification of potential data sharing locations

A method for testing the correct behavior of an integrated circuit includes forming a list of potential data sharing locations, collecting memory access statistics of the potential data sharing locations, and forming subsequent test case threads to test specialized processing conditions of the integrated circuit based on the memory access statistics of the potential data sharing locations.

Method and apparatus for tracking memory access statistics for data sharing applications

Systems, methodologies, media, and other embodiments associated with a system for producing a bus-type header-type field from a point-to-point data-type field are described. One exemplary system embodiment includes a logic configured to identify that a point-to-point transaction includes non-memory-data information encoded in a data flit, a logic configured to extract the non-memory-data information from the data flit, and a logic configured to produce a header-type field for a bus-type transaction produced by the virtual bus interface from the point-to-point transaction.

Virtual bus interface production of header-type fields from data-type fields

A system and method for building a test case operable to test a circuit design, the test case including a summary of instructions. In one embodiment, an instruction generation engine generates a set of instructions of which at least one instruction includes a temporarily uncommitted value. A first summary generation engine portion generates an interfaceable enumeration of the set of instructions wherein each of the temporarily uncommitted values is denoted by an uncommitted reference. A second summary generation engine portion resolves the respective values of the uncommitted references and generates an interfaceable listing of the uncommitted references and their the respective values. The set of instructions and the interfaceable listing of the resolved uncommitted references may be arranged to form the test case.

System and method for building a test case including a summary of instructions

Method and system for automatically backtracing through a testcase file. First the testcase file is accessed. Next, a start line identifier for specifying an instruction line in the testcase file at which to begin processing is received. The instruction line in the testcase file that is specified by the start line identifier is processed first. The previous instruction lines in the testcase file are then processed in a sequential fashion until the beginning of the testcase file is reached.

Automated method and system for backtracing of instruction parameters from specified instruction in test cases

Techniques are disclosed for initializing a representation of a cache in a microprocessor design under test. The cache representation includes a plurality of cache entries, each of which is uniquely referenced by an address-way pair. A test case includes a plurality of cache initialization records, each of which includes a cache entry reference and an initial cache entry value. Each cache entry reference includes an address identifier and a way identifier. An initializer reads the cache initialization records and uses the records which contain valid address-way pairs to initialize cache entries in the cache representation. The initializer then uses the remaining records, in which the way identifier is an invalid (e.g., null) value, to initialize cache entries in the cache representation. Valid way identifiers are selected for these records in a manner which ensures that cache entries are not initialized more than once.

Microprocessor cache design initialization

A system for detecting/avoiding memory usage conflicts when generating and merging multi-threaded software test cases. Initially, a test case generator is given a unique segment of memory which it can use. A plurality of test cases are generated, one at a time, by the test case generator. When the first test case is generated, the memory segment used is noted. When each of the second through Nth test cases is generated, a memory segment of the same size as the first test case, but not overlapping that of the previously assigned test case(s), is assigned to each subsequent test case.

System for preventing memory usage conflicts when generating and merging computer architecture test cases

A method of converting a testcase designed to execute on a first member of a processor family to a converted testcase for execution on a second member of a processor family provides particularly for conversion of Translation Lookaside Buffer usage. The method is operable on a computer. The method involves automatically comparing each TLB location used by the testcase to TLB locations available in the second member of the processor family, or, if the second member of the processor family is a multiprocessor circuit, a standard partition available in the second member of the processor family. If the testcase uses only TLB locations that are available in the second member of the processor family, indicating that the testcase is runable on the second member of the processor family. In particular embodiments, TLB locations used by the testcase are automatically reassigned to locations available in the TLB, or standard partition of the TLB, in the second member of the processor family.

Growing community of inventors

Loveland, CO, United States of America

Ryan Clarence Thompson