Taiwan Semiconductor Manufacturing Comp. Ltd.

Ryan Chia-jen Chen

Ming-Ching Chang

Yi-Chun Chen

Yu-Hsien Lin

Yuan-Sheng Huang

I-Wei Yang

Tzu-Wen Pan

Shu-Yuan Ku

Chih-Chang Hung

Li-Wei Yin

Yih-Ann Lin

Ya-Yi Tsai

Yi-Hsuan Hsiao

An Chyi Wei

Cheng-Chung Chang

Chen-Huang Huang

Ming-Chia Tai

Ming-Jhe Sie

Shao-Hua Hsu

Chia Ming Liang

Jih-Jse Lin

Shun-Hui Yang

Chao-Hsuan Chen

Jih-Sheng Yang

Shih-Chieh Chao

Y L Cheng

A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first channel and a second gate segment is disposed over the second channel. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Metal gate structure and methods of fabricating thereof

Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Tunable structure profile

A method includes: receiving a substrate; depositing a first gate layer over the substrate; patterning the first gate layer to form a first gate stack and leaving at least one void exposed from a sidewall of the first gate stack; depositing a dielectric layer on the sidewall of the first gate stack; and removing a first portion of the dielectric layer from the sidewall of the first gate stack while leaving a second portion of the dielectric layer to fill the at least one void.

Semiconductor structure and method of manufacturing the same

Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

Multipatterning gate processing

A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

Air spacers around contact plugs and method forming same

A method incudes forming first and second semiconductor fins upwardly extending from a substrate; forming a gate strip extending across the first and second semiconductor fins; growing first source/drain regions on the first semiconductor fin and at opposite sides of the gate strip, second source/drain regions on the second semiconductor fin and at opposite sides of the gate strip; depositing a dielectric layer over the first and second source/drain regions; forming an isolation material in the dielectric layer and between one of the first source/drain regions and one of the second source/drain regions; performing an etching process on the isolation material and the gate strip to form an opening, the opening breaking the grid strip and recessing the isolation material; forming a separation material in the opening.

Method for fabricating semiconductor structure with cutting depth control

A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Fin field-effect transistor and method of forming the same

A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.

A semiconductor structure and method for fabricating a semiconductor structure includes using two separate oxide layers to improve device reliability. A first oxide layer is formed adjacent a fin (e.g. a fin of a fin field-effect transistor (FinFET) device), a dummy gate is formed adjacent the first oxide layer, the dummy gate is removed, and a second oxide layer is then formed adjacent the first oxide layer. The use of the second oxide layer can improve device reliability by covering any damage that may be inflicted on the first oxide layer when the dummy gate is removed.

Semiconductor structure with composite oxide layer

A semiconductor structure includes a first device and a second device. The first device includes a plurality of first fins, a first work function layer over the plurality of first fins, and a first contact layer over the first work function layer. The second device includes a plurality of second fins, a second work function layer and the first work function layer over the plurality of the second fins, and a second contact layer over the first work function layer and the second work function layer. A distance between a bottom surface of the first work function layer and a bottom surface of the first contact layer is greater than a distance between a side surface of the first work function layer of the first device and a side surface of the first contact layer.

Fin field effect transistor devices including NMOS device and PMOS device with varied geometry of work function layers

Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Semiconductor structure cutting process and structures formed thereby

An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

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HSINCHU, Taiwan

Ryan Chia-jen Chen