Taiwan Semiconductor Manufacturing Comp. Ltd.

Ryan Chia-Jen Chen

Yih-Ann Lin

Chao-Cheng Chen

Ming-Ching Chang

Shu-Yuan Ku

Kuo-Tai Huang

Yu Chao Lin

Ya-Yi Tsai

Shu-Uei Jang

Jr Jung Lin

Yi-Hsing Chen

Yuan-Sheng Huang

Chien-Hao Chen

Shiang-Bau Wang

Yi-Shien Mor

Chen-Huang Huang

An Chyi Wei

Cheng-Chung Chang

Chia Tai Lin

Yi-Chun Chen

Chih-Chang Hung

Ming-Jhe Sie

Bao-Ru Young

Chia-Wei Chang

Yi-Hsuan Hsiao

I-Wei Yang

Donald Y Chao

Shao-Hua Hsu

Li-Wei Yin

Chih-Tang Peng

Yu-Hsien Lin

Chung-Shu Wu

An-Chyi Wei

Shun-Hui Yang

Kuo-Cheng Ching

Hui-Wen Lin

Ting-Hua Hsieh

Chih-Han Lin

Carlos H Diaz

Ming Zhu

Tai-Chun Huang

Yu-Chao Lin

Ming-Jie Huang

An-Shen Chang

Jih-Jse Lin

Chin-Hsiang Lin

Harry-Hak-Lay Chuang

Mong-Song Liang

Hun-Jan Tao

Chi-Ming Yang

Jr-Jung Lin

Kuo-Bin Huang

Harry Hak-Lay Chuang

Chyi Shyuan Chern

Yuan-Hung Chiu

Chi-Chun Chen

Fang-Cheng Chen

Matt Yeh

Shun Wu Lin

Kuo Bin Huang

Chieh-Ning Feng

Syun-Ming Jang Jang

Chi On Chui

Tze-Liang Lee

Kong-Beng Thei

Harry Chuang

Po-Chi Wu

Cheng-Han Wu

Jin-Aun Ng

Chunyao Wang

Kang-Cheng Lin

Hsiu-Hao Tsao

Wen-Shuo Hsieh

Joshua Tseng

Ji-Yi Yang

Ching-Yu Chang

Che-Cheng Chang

Li-Te S Lin

Weng Chang

Kuei-Shun Chen

Chun-Hung Lee

De-Fang Chen

Chen-Nan Yeh

Sheng-Chen Chung

Chia-Chu Liu

Hao-Ming Lien

Hua Feng Chen

Ju-Wang Hsu

Yu-Wen Wang

Wen-Huei Guo

Jung-Hui Kao

Tzu-Yen Hsieh

Mong Song Liang

Chi-Kang Chang

Ming-Chia Tai

Su-Chen Lai

Chung-Long Cheng

Lung-Kai Mao

Shih-Chiang Chen

Gary Shen

Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Residue-free metal gate cutting for fin-like field effect transistor

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

Fin field-effect transistor devices and methods of forming the same

A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Methods for forming fin field-effect transistors

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Semiconductor structure having dielectric structure extending into second cavity of semiconductor Fin

A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.

Fin field-effect transistor and method of forming the same

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The method includes receiving a substrate with fin features; forming a first gate stack over the substrate, wherein the first gate stack comprise at least one void exposed from a surface of the first gate stack; forming a fill material in the at least one void; partially removing the fill material outside the at least one void, wherein a portion of the fill material is left in the at least one void; forming sidewall spacers besides the first gate stack; removing the first gate stack; and forming a second gate stack.

Semiconductor structure and method of manufacturing the same

A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

Air spacers around contact plugs and method forming same

A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

Gate stacks for semiconductor devices of different conductivity types

A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having fin structures. The substrate includes a material having a substrate thermal expansion coefficient. The semiconductor structure also includes an isolation structure between the fin structures. The isolation structure includes a first dielectric material and a second dielectric material. The first dielectric material has a first thermal expansion coefficient and the second dielectric material has a second thermal expansion coefficient. The substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.

Semiconductor structure having isolations between fins and comprising materials with different thermal expansion coefficients (CTE)

A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Semiconductor device and method of manufacture

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

Cut metal gate processes

A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Nanostructure field-effect transistor device and method of forming

A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Method for forming fin field effect transistor (FinFET) device structure

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Chiayi, Taiwan

Ryan Chia-Jen Chen